参数资料
型号: HI20201-EV
厂商: Intersil Corporation
英文描述: 10-Bit, 160 MSPS, Ultra High Speed D/A Converter
中文描述: 10位,160 MSPS的,超高速D / A转换
文件页数: 9/11页
文件大小: 82K
代理商: HI20201-EV
10-1205
FIGURE 11. MAXIMUM CONVERSION RATE, RISE TIME, FALL TIME, PROPAGATION DELAY, SETUP TIME, HOLD TIME AND
SETTLING TIME CIRCUIT
Measuring Settling Time
Settling time is measured as follows. The relationship
between V and V
0(FS)
as shown in the D/A output waveform
in Figure 12 is expressed as
V = V
0(FS)
(1 - e
-t
τ
).
The settling time for respective accuracy of 10, 9 and 8-bit is
specified as
V = 0.9995 V
0(FS)
V = 0.999 V
0(FS)
V = 0.999 V
0(FS)
which results in the following:
t
S
= 7.60
τ
for 10-bit,
t
S
= 6.93
τ
for 9-bit, and
t
S
= 6.24
τ
for 8-bit,
Rise time (t
r
) and fall time (t
f
) are defined as the time interval
to slew from 10% to 90% of full scale voltage (V
0(FS)
):
V = 0.1 V
0(FS)
V = 0.9 V
0(FS)
and calculated as t
r
= t
f
= 2.20
τ
.
The settling time is obtained by combining these expressions:
t
S
= 3.45t
r
for 10-bit,
t
S
= 3.15t
r
for 9-bit, and
t
S
= 6.24t
r
for 8-bit
FIGURE 12. D/A OUTPUT WAVEFORM
Test Circuits
(Continued)
28
27
26
25
24
23
22
21
20
19
18
17
16
15
1
2
3
4
5
6
7
8
9
10
11
12
13
14
D
Q
Q
CLKF
-5.2V
131
82
82
131
-5.2V
1
/
6
HD100151
CLKF
A
82
131
82
131
-5.2V
1
131
470
131
82
1
DL
1
-1.3V
-1.3V
TO PG
50
HD100116
B
-5.2V
C
39
100
TO SCOPE
50
-5.2V
OUT
CLK
CLK
LSB
MSB
DL: Delay line
Capacitors are 0.047
μ
F ceramic chip capacitors unless otherwise specified.
10k
V
V
0(FS)
= 1V
τ
τ
HI20201
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