参数资料
型号: HI20201
厂商: Intersil Corporation
英文描述: 10-Bit, 160 MSPS, Ultra High Speed D/A Converter
中文描述: 10位,160 MSPS的,超高速D / A转换
文件页数: 6/11页
文件大小: 82K
代理商: HI20201
10-1202
Detailed Description
The HI20201 is a 10-bit, current output D/A converter. The
DAC can run at 160MHz and is ECL compatible. The archi-
tecture is segmented/R2R combination to reduce glitch and
improve linearity.
Architecture
The HI20201 is a combined R2R/segmented current source
design. The 6 least significant bits of the converter are
derived by a traditional R2R network to binary weight the
1mA current sources. The upper 4 most significant bits are
implemented as segmented or thermometer encoded cur-
rent sources. The encoder converts the incoming 4 bits to 15
control lines to enable the most significant current sources.
The thermometer encoder will convert binary to individual
control lines. See Table 1.
The architecture of the HI20201 is designed to minimize
glitch while providing a manufacturable 10-bit design that
does not require laser trimming to achieve good linearity.
Glitch
Glitch is caused by the time skew between bits of the
incoming digital data. Typically the switching time of digital
inputs are asymmetrical meaning that the turn off time is
faster than the turn on time (TTL designs). In an ECL system
where the logic levels switch from one non-saturated level to
another, the switching times can be considered close to
symmetrical. This helps to reduce glitch in the D/A. Unequal
delay paths through the device can also cause one current
source to change before another. To minimize this the Intersil
HI20201 employs an internal register, just prior to the current
sources, that is updated on the clock edge. Lastly the worst
case glitch usually happens at the major transition i.e.,
01 1111 1111 to 10 0000 0000. But in the HI20201 the glitch
is moved to the 00 0001 1111 to 11 1110 0000 transition.
This is achieved by the split R2R/segmented current source
architecture. This decreases the amount of current switching
at any one time and makes the glitch practically constant
over the entire output range. By making the glitch a constant
size over the entire output range this effectively integrates
this error out of the end application.
In measuring the output glitch of the HI20201 the output is
terminated into a 75
load. The glitch is measured at the
major carry’s throughout the DAC’s output range.
The glitch energy is calculated by measuring the area under
the voltage-time curve. Figure 7 shows the area considered
as glitch when changing the DAC output. Units are typically
specified in picoVolt/seconds (pV/s).
Setting Full Scale
The full scale output voltage is set by the Voltage Reference
pin (27). The output voltage performance will vary as shown
in Figure 2.
The output structure of the HI20201 can handle down to a
75
load effectively. To drive a 50
load Figure 8 is sug-
gested. Note the equivalent output load is ~75
.
TABLE 1. THERMOMETER ENCODER
MSB
BIT 8
BIT 7
BIT 6
THERMOMETER CODE
1 = ON, 0 = OFF, I
15
- I
0
000 0000 0000 0000
0
0
0
0
0
0
0
1
000 0000 0000 0001
0
0
1
0
000 0000 0000 0011
0
0
1
1
000 0000 0000 0111
0
1
0
0
000 0000 0000 1111
0
1
0
1
000 0000 0001 1111
0
1
1
0
000 0000 0011 1111
0
1
1
1
000 0000 0111 1111
1
0
0
0
000 0000 1111 1111
1
0
0
1
000 0001 1111 1111
1
0
1
0
000 0011 1111 1111
1
0
1
1
000 0111 1111 1111
1
1
0
0
000 1111 1111 1111
1
1
0
1
001 1111 1111 1111
1
1
1
0
011 1111 1111 1111
1
1
1
1
111 1111 1111 1111
(20) I
OUT
34MHz
LOW PASS
FILTER
75
50
SCOPE
HI20201
FIGURE 6. HI20201 GLITCH TEST CIRCUIT
A (mV)
t (ns)
GLITCH ENERGY = (a x t)/2
FIGURE 7. GLITCH ENERGY
HI20201
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