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参数资料
| 型号： | HI20206JCP |
| 厂商： | INTERSIL CORP |
| 元件分类： | DAC |
| 英文描述： | Triple 8-Bit, 35 MSPS, RGB, 3-Channel D/A Converter |
| 中文描述： | PARALLEL, 8 BITS INPUT LOADING, 0.016 us SETTLING TIME, 8-BIT DAC, PDIP42 |
| 封装： | PLASTIC, DIP-42 |
| 文件页数： | 6/13页 |
| 文件大小： | 171K |
| 代理商： | HI20206JCP |
10-6
Glitch Energy
GE
V
SET
- AGND = 0.8V,
R
L
>10k
, f
CLK
= 1MHz,
Digital Ramp Output,
See Figure 6 (Note 5)
-
160
-
pV/s
Rise Time (Note 6)
t
r
t
f
V
SET
- AGND = 0.8V
See Figure 4
-
5.5
-
ns
Fall Time (Note 6)
-
5.0
-
ns
Settling Time
t
SET
-
16
-
ns
NOTES:
3. AV
CC
- V
O
.
4. Maximum value among
.
5. Observe the glitch which is generated when the digital input varies as follows:
0
0
1 1
1
1
1
1
— 0
1
01 1
1 1
1
1
1
1
— 1
0
10 1
1 1
1
1
1
1
— 1
1
6. The time required for the D/A OUT to arrive at 90% of its final value from 10%.
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Electrical Specifications
T
A
= 25
o
C, AV
CC
= DV
CC
= 5V, AGND = DGND = 0V
(Continued)
PARAMETER
SYMBOL
TEST
CONDITIONS
MIN
TYP
MAX
UNITS
100
V
OFS G
)
-----------------------
1
–
×
, 100
V
OFS B
)
-----------------------
1
–
, or 100
V
OFS R
-----------------------
1
–
×
×
INPUT CORRESPONDING TABLE
INPUT CODE
OUTPUT VOLTAGE
MSB
LSB
1 1 1 1 1 1 1 1
1 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
V
CC
+ V
OFFSET
V
CC
+ V
OFFSET
-0.5V
V
CC
+ V
OFFSET
-1.0V
NOTE: In case the output voltage full scale is 1V (1 LSB = 3.92mV).
Test Circuits
FIGURE 1. DIFFERENTIAL LINEARITY AND INTEGRAL LINEARITY TEST CIRCUITS
37
35
ROUT
V
33
GOUT
31
29
BOUT
AV
CC
V
REF
V
SET
+
-
27
26
25
V
22
39 - 42
1 ~ 4
D1 ~ D8
8 (R)
D1 ~ D8
8 (G)
D1 ~ D8
8 (B)
5 ~ 12
13 ~ 20
21
CLK
CLK TTL LEVEL
HI20206
DV
CC
DGND
D8
D2
D1
33
μ
F
3K
HI20206
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