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参数资料
| 型号： | HI3-774K-5 |
| 厂商： | INTERSIL CORP |
| 元件分类： | ADC |
| 英文描述： | Complete, 12-Bit A/D Converters with Microprocessor Interface |
| 中文描述： | 1-CH 12-BIT SUCCESSIVE APPROXIMATION ADC, PARALLEL ACCESS, PDIP28 |
| 封装： | PLASTIC, DIP-28 |
| 文件页数： | 15/18页 |
| 文件大小： | 200K |
| 代理商： | HI3-774K-5 |
6-966
The 12/8 input will be tied high or low in most applications,
though it is fully TTL/CMOS-compatible. With 12/8 high, all
12 output lines become active simultaneously, for interface to
a 12-bit or 16-bit data bus. The A
O
input is ignored.
With 12/8 low, the output is organized in two 8-bit bytes,
selected one at a time by A
O
. This allows an 8-bit data bus
to be connected as shown in Figure 6. A
O
is usually tied to
the least significant bit of the address bus, for storing the
HI-X74(A) output in two consecutive memory locations.
(With A
O
low, the 8 MSBs only are enabled. With A
O
high, 4
MSBs are disabled, bits 4 through 7 are forced low, and the 4
LSBs are enabled). This two byte format is considered “left
justified data,” for which a decimal (or binary!) point is
assumed to the left of byte 1:
Further, A
O
may be toggled at any time without damage to
the converter. Break-before-make action is guaranteed
between the two data bytes, which assures that the outputs
strapped together in Figure 6 will never be enabled at the
same time.
A read operation usually begins after the conversion is
complete and STS is low. For earliest access to the data,
however, the read should begin no later than (t
DD
+ t
HS
)
before STS goes low. See Figure 5.
BYTE 1
BYTE 2
X
X
X
X
X
X
X
X
X
X
X
X
0
0
0
0
MSB
LSB
See HI-774 Timing Specifications for more information.
FIGURE 4. CONVERT START TIMING
CE
CS
R/C
A
O
STS
DB11-DB0
t
SSC
t
SRC
t
HEC
t
HSC
t
SAC
t
HAC
t
DSC
t
C
HIGH IMPEDANCE
t
HRC
See HI-774 Timing Specifications for more information.
FIGURE 5. READ CYCLE TIMING
FIGURE 6. INTERFACE TO AN 8-BIT DATA BUS
CE
CS
R/C
A
O
STS
DB11-DB0
HIGH IMPEDANCE
t
DD
t
SSR
t
SRR
t
SAR
t
HS
t
HD
t
HL
t
HAR
t
HRR
t
HSR
DATA
VALID
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
STS
DB11 (MSB)
DB0 (LSB)
DIG.
COM.
HI-774
12/8
A
O
A
O
DATA
BUS
ADDRESS BUS
HI-574A, HI-674A, HI-774
相关PDF资料 |
PDF描述 |
|---|---|
| HI1-774K-5 | Complete, 12-Bit A/D Converters with Microprocessor Interface |
| HI1-574AKD-5 | Complete, 12-Bit A/D Converters with Microprocessor Interface |
| HI1-674AKD-5 | Complete, 12-Bit A/D Converters with Microprocessor Interface |
| HI-674A | 128 MACROCELL 3.3 VOLT ISP CPLD - NOT RECOMMENDED for NEW DESIGN |
| HI-774 | 128 MACROCELL 3.3 VOLT ISP CPLD |
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