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参数资料
| 型号： | HI3256 |
| 厂商： | Intersil Corporation |
| 英文描述： | 8-Bit, 120MSPS, Flash A/D Converter(8位、120MSPS 闪存A/D转换器) |
| 中文描述： | 8位，120MSPS，闪光的A / D转换器（8位，120MSPS闪存的A / D转换器） |
| 文件页数： | 10/15页 |
| 文件大小： | 175K |
| 代理商： | HI3256 |
3-10
Operating Modes
The HI3256 has two types of operating modes which are selected with Pin 45 (SELECT1).
DMUX Mode (See Application Circuits,
Figures 18, 19)
Set the SELECT1 pin to V
CC
for this mode. In this mode, the
clock frequency is divided by 2 in the IC, and the data is
output after being demultiplexed by this
1
/
2
frequency
divided clock. The
1
/
2
frequency divided clock, which has
adequate setup time and hold time for the output data, is
output from the CLKOUT pin.
When using multiple HI3256 units in parallel in this mode,
differences in the start timing of the
1
/
2
frequency divided clock
may cause operation as shown in Figure 9. As a
countermeasure, the HI3256 is equipped with a function which
resets the
1
/
2
frequency divided clock. When resetting this
clock, the RESET pulse must be input to the RESET pin. See
the Timing Charts for the RESET pulse input timing. The A/D
converter can operate at f
C
(Min) = 120MSPS in this mode.
Straight Mode (See Application Circuits, Figures
20, 21)
Set the SELECT1 pin to GND for this mode. In this mode,
data output can be obtained in accordance with the clock
frequency applied to the A/D converter for applications which
use the clock applied to the A/D converter as the system clock.
The A/D converter can operate at f
C
(Min) = 100MSPS in
this mode.
Digital Input Level and Supply Voltage Settings
The logic input level for the HI3256 supports PECL and TTL
levels.
The power supplies (DV
EE3
, DGND3) for the logic input
block must be set to match the logic input (CLK and RESET
signals) level.
FIGURE 6. ERROR RATE MEASUREMENT CIRCUIT
FIGURE 7. SAMPLING DELAY/APERTURE JITTER
MEASUREMENT CIRCUIT
NOTE: Where
σ
(LSB) is the deviation of the output codes when the
largest slew rate point is sampled at the clock which has exactly the
same frequency as the analog input signal, the aperture jitter t
AJ
is:
FIGURE 8. APERTURE JITTER MEASUREMENT METHOD
Test Circuits
(Continued)
SIGNAL
SOURCE
COMPARATOR
A > B
PULSE
COUNTER
SIGNAL
SOURCE
LATCH
+
1
/
8
LATCH
A
f
C
4
B
8
16 LSB
2V
P-P
SINE WAVE
-1kHz
V
IN
CLK
CLK
f
C
HI3256
LOGIC
ANALYZER
HI3256
V
IN
CLK
AMP
8
1024
SAMPLES
PECL
BUFFER
OSC1
φ
: VARIABLE
OSC2
100MHz
f
R
100MHz
V
RT
V
RM2
V
RB
129
128
127
126
125
(LSB)
υ
t
σ
V
IN
CLK
V
IN
CLK
SAMPLING TIMING FLUCTUATION
(= APERTURE JITTER)
t
AJ
=
σ
/
t
-------
=
σ
/22
x 2
π
f
.
TABLE 2. OPERATING MODE
OPERATING
MODE
SELECT1
MAXIMUM
CONVERSION RATE
DATA OUTPUT
CLOCK OUTPUT
DMUX Mode
V
CC
120MSPS
Demultiplexed Output 60MBPS
The input clock is
1
/
2
frequency divided and output at
60MHz.
Straight Mode
GND
100MSPS
Straight Output 100MBPS
The input clock is inverted and output at 100MHz.
HI3256
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