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参数资料
| 型号： | HI3286JCQ |
| 厂商： | INTERSIL CORP |
| 元件分类： | ADC |
| 英文描述： | 8-Bit, 160MSPS, Flash A/D Converter |
| 中文描述： | 1-CH 8-BIT FLASH METHOD ADC, PARALLEL ACCESS, PQFP48 |
| 封装： | 7 X 7 MM, PLASTIC, LQFP-48 |
| 文件页数： | 7/16页 |
| 文件大小： | 229K |
| 代理商： | HI3286JCQ |
7
16
SELECT2
I
DV
CC1
, DGND1 or Open
Data output switching. Data is output
from both PA and PD when left open.
If pin is connected to
DV
CC1
, only PA
is used as output with PB high
impedance. If pin is connected to
DGND1
,onlyPBisusedasoutputwith
PA high impedance.
17
VOCLP
I
Clamp Voltage
Defines TTL output high level. If left
open the high level is ~ 2.8V.
18
PS
I
TTL
Power Savings pin. When left open or
at high level the device operates
normally. When set to low level the
power saving mode enabled.
13
CLK/E
I
PECL/ECL
Clock Input.
14
CLK/NE
I
CLK/E Complementary Input. When
left open, this pin goes to the threshold
potential. Only CLK/E can be used for
operation, but complementary input is
recommended to attain fast and stable
operation.
48
RESETN/E
I
Reset Input. When the input is set to
low level, the built-in CLK frequency
divider circuit can be reset.
47
RESET/E
I
RESETN/E Complementary Input.
When left open, this pin goes to the
threshold voltage. Only RESETN/E
can be used for operation.
15
CLK/T
I
TTL
Clock input.
46
RESETN/T
I
Reset Input. When left open, this
input goes to high level. When the
input is set to low level, the built-in
CLK frequency divider circuit can be
reset.
44
INV
I
TTL
Data Output Polarity Inversion Input.
When left open, this input goes to high
level. (See Table 1; I/O
Correspondence Table).
Pin Descriptions
(Continued)
PIN
NO
SYMBOL
I/O
TYPICAL
VOLTAGE LEVEL
EQUIVALENT CIRCUIT
DESCRIPTION
13 48
DGND3
DV
EE3
47
14
46
15
DV
CC1
1.5V
OR
,
DGND1
DV
EE3
44
45
44
DV
CC1
DGND1
DV
EE3
HI3286
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