参数资料
型号: HI3338KIB
厂商: Intersil
文件页数: 8/9页
文件大小: 0K
描述: IC DAC 8BIT CMOS R-R 16-SOIC
标准包装: 48
设置时间: 20ns
位数: 8
数据接口: 并联
转换器数目: 1
电压电源: 单电源
功率耗散(最大): 100mW
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 16-SOIC(0.295",7.50mm 宽)
供应商设备封装: 16-SOIC
包装: 管件
输出数目和类型: 1 电压,单极;1 电压,双极
采样率(每秒): 50M
8
Applications
The output of the HI3338 can be resistively divided to match
a doubly terminated 50
or 75 line, although peak-to-peak
swings of less than 1V may result. The output magnitude will
also vary with the converter's output impedance. Figure 5
shows such an application. Note that because of the HCT
input structure, the HI3338 could be operated up to +7.5V
VDD and VREF+ supplies and still accept 0V to 5V CMOS
input voltages.
If larger voltage swings or better accuracy is desired, a high
speed output buffer, such as the HA-5033, HA-2542, or
CA3450, can be employed. Figure 6 shows a typical
application, with the output capable of driving
±2V into
multiple 50
terminated lines.
Operating and Handling Considerations
HANDLING
All inputs and outputs of CMOS devices have a network for
electrostatic protection during handling. Recommended
handling practices for CMOS devices are described in
AN6525. “Guide to Better Handling and Operation of CMOS
Integrated Circuits.”
OPERATING
OPERATING VOLTAGE
During operation near the maximum supply voltage limit,
care should be taken to avoid or suppress power supply
turn-on and turn-off transients, power supply ripple, or
ground noise; any of these conditions must not cause the
absolute maximum ratings to be exceeded.
INPUT SIGNALS
To prevent damage to the input protection circuit, input
signals should never be greater than VDD nor less than VSS.
Input currents must not exceed 20mA even when the power
supply is off.
UNUSED INPUTS
A connection must be provided at every input terminal. All
unused input terminals must be connected to either VCC or
GND, whichever is appropriate.
NOTES:
1. Both VREF+ pin and 392 resistor should be bypassed within
1/
4 inch.
2. Keep nodal capacitance at CA3450 pin 3 as low as possible.
3. VOUT Range = ±3V at CA3450.
CLOCK
8 DATA
+5V
15
16
14
8
1-7, 9
LE
D0 - D7
VDD
COMP
VSS
HI3338
VOUT
VREF+
VEE
12
13
11
10
R
VREF-
R
11
UP TO 5 OUTPUT LINES
FOR R = 75
, 3 LINES
FOR R = 50
VOUT1
VOUTN
+3.00V AT 25mA
4.7
F
TAN
4.7
F TAN
4.7
F
TAN
0.1
F
CER.
0.1
F
CER.
0.1
F CER.
14
+6V
-6V
392
392
1%
10k
1k
3
4, 5, 12, 13
R
+
VOUT = ± 1.5VPEAK
6
7, 8
9
+
-
CA3450
ADJUST
OFFSET
5pF
BITS
1%
4.7
F
TAN
0.1
F
CER.
FIGURE 6. HI3338 AND CA3450 FOR DRIVING MULTIPLE COAXIAL LINES
HI3338
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