参数资料
型号: HI5766KCA
厂商: Intersil
文件页数: 5/16页
文件大小: 0K
描述: IC ADC 10-BIT 60MSPS 28-SSOP
标准包装: 48
位数: 10
采样率(每秒): 60M
数据接口: 并联
转换器数目: 8
功率耗散(最大): 260mW
电压电源: 模拟和数字
工作温度: 0°C ~ 70°C
安装类型: 表面贴装
封装/外壳: 28-SSOP(0.154",3.90mm 宽)
供应商设备封装: 28-SSOP/QSOP
包装: 管件
输入数目和类型: 2 个单端,单极;1 个差分,双极
13
The resistors, R, in Figure 26 are not absolutely necessary
but may be used as load setting resistors. A capacitor, C,
connected from VIN+ to VIN- will help filter any high
frequency noise on the inputs, also improving performance.
Values around 20pF are sufficient and can be used on AC
coupled inputs as well. Note, however, that the value of
capacitor C chosen must take into account the highest
frequency component of the analog input signal.
Analog Input, Single-Ended Connection
The configuration shown in Figure 27 may be used with a
single ended AC coupled input.
Again, assume the difference between VREF+, typically
2.5V, and VREF-, typically 2V, is 0.5V. If VIN is a 1VP-P
sinewave, then VIN+ is a 1VP-P sinewave riding on a
positive voltage equal to VDC. The converter will be at
positive full scale when VIN+ is at VDC + 0.5V (VIN+ - VIN-
= +0.5V) and will be at negative full scale when VIN+ is
equal to VDC - 0.5V (VIN+ - VIN- = -0.5V). Sufficient
headroom must be provided such that the input voltage
never goes above +5V or below AGND. In this case, VDC
could range between 0.5V and 4.5V without a significant
change in ADC performance. The simplest way to produce
VDC is to use the DC bias source, VDC, output of the
HI5766.
The single ended analog input can be DC coupled
(Figure 28) as long as the input is within the analog input
common mode voltage range.
The resistor, R, in Figure 28 is not absolutely necessary but
may be used as a load setting resistor. A capacitor, C,
connected from VIN+ to VIN- will help filter any high
frequency noise on the inputs, also improving performance.
Values around 20pF are sufficient and can be used on AC
coupled inputs as well. Note, however, that the value of
capacitor C chosen must take into account the highest
frequency component of the analog input signal.
A single ended source may give better overall system
performance if it is first converted to differential before driving
the HI5766.
Digital Output Control and Clock Requirements
The HI5766 provides a standard high-speed interface to
external TTL logic families.
In order to ensure rated performance of the HI5766, the duty
cycle of the clock should be held at 50%
±5%. It must also
have low jitter and operate at standard TTL levels.
Performance of the HI5766 will only be guaranteed at
conversion rates above 1 MSPS. This ensures proper
performance of the internal dynamic circuits. Similarly, when
power is first applied to the converter, a maximum of 20
cycles at a sample rate above 1 MSPS will have to be
performed before valid data is available.
A Data Format Select (DFS) pin is provided which will
determine the format of the digital data outputs. When at
logic low, the data will be output in offset binary format.
When at logic high, the data will be output in two’s
complement format. Refer to Table 1 for further information.
VIN+
VIN-
HI5766
VIN
VDC
R
FIGURE 27. AC COUPLED SINGLE ENDED INPUT
VIN+
VIN-
HI5766
VDC
R
C
VIN
VDC
FIGURE 28. DC COUPLED SINGLE ENDED INPUT
HI5766
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