参数资料
| 型号： | HI5767/4CB |
| 厂商： | Intersil |
| 文件页数： | 7/15页 |
| 文件大小： | 0K |
| 描述： | CONV A/D 10BIT 40MSPS 28-SOIC |
| 标准包装： | 26 |
| 位数： | 10 |
| 采样率（每秒）： | 40M |
| 数据接口： | 并联 |
| 转换器数目： | 8 |
| 功率耗散（最大）： | 310mW |
| 电压电源： | 模拟和数字 |
| 工作温度： | 0°C ~ 70°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 28-SOIC（0.295"，7.50mm 宽） |
| 供应商设备封装： | 28-SOIC W |
| 包装： | 管件 |
| 输入数目和类型： | 2 个单端，单极；1 个差分，双极 |
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Video Definitions
Differential Gain and Differential Phase are two commonly
found video specifications for characterizing the distortion of
a chrominance signal as it is offset through the input voltage
range of an ADC.
Differential Gain (DG)
Differential Gain is the peak difference in chrominance
amplitude (in percent) relative to the reference burst.
Differential Phase (DP)
Differential Phase is the peak difference in chrominance
phase (in degrees) relative to the reference burst.
Timing Definitions
Refer to Figure 1 and Figure 2 for these definitions.
Aperture Delay (tAP)
Aperture delay is the time delay between the external
sample command (the falling edge of the clock) and the time
at which the signal is actually sampled. This delay is due to
internal clock path propagation delays.
Aperture Jitter (tAJ)
Aperture jitter is the RMS variation in the aperture delay due
to variation of internal clock path delays.
Data Hold Time (tH)
Data hold time is the time to where the previous data (N - 1)
is no longer valid.
Data Output Delay Time (tOD)
Data output delay time is the time to where the new data (N)
is valid.
Data Latency (tLAT)
After the analog sample is taken, the digital data representing
an analog input sample is output to the digital data bus on
the 7th cycle of the clock after the analog sample is taken.
This is due to the pipeline nature of the converter where the
analog sample has to ripple through the internal subconverter
stages. This delay is specified as the data latency. After the
data latency time, the digital data representing each
succeeding analog sample is output during the following
clock cycle. The digital data lags the analog input sample by 7
sample clock cycles.
Power-Up Initialization
This time is defined as the maximum number of clock cycles
that are required to initialize the converter at power-up. The
requirement arises from the need to initialize the dynamic
circuits within the converter.
HI5767
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相关代理商/技术参数 |
参数描述 |
|---|---|
| HI5767EVAL1 | 功能描述:数据转换 IC 开发工具 HI5767 LW FREQUENCY EVALUATION PLATFORM RoHS:否 制造商:Texas Instruments 产品:Demonstration Kits 类型:ADC 工具用于评估:ADS130E08 接口类型:SPI 工作电源电压:- 6 V to + 6 V |
| HI5767EVAL2 | 功能描述:数据转换 IC 开发工具 HI5767 HI FREQUENCY EVALUATION PLATFORM RoHS:否 制造商:Texas Instruments 产品:Demonstration Kits 类型:ADC 工具用于评估:ADS130E08 接口类型:SPI 工作电源电压:- 6 V to + 6 V |
| HI5780 | 制造商:INTERSIL 制造商全称:Intersil Corporation 功能描述:10-Bit, 80 MSPS, High Speed, Low Power D/A Converter |
| HI5780-EV | 制造商:INTERSIL 制造商全称:Intersil Corporation 功能描述:10-Bit, 80 MSPS, High Speed, Low Power D/A Converter |
| HI5780JCQ | 制造商:Rochester Electronics LLC 功能描述:32 PQFP COMTEMP VIDEO D/A 10BIT 80MHZ - Bulk 制造商:Harris Corporation 功能描述: |
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