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参数资料
| 型号： | HI7131CPL |
| 厂商： | INTERSIL CORP |
| 元件分类： | ADC |
| 英文描述： | 3 1/2 Digit, Low Power, High CMRR, LCD/LED Display-Type A/D Converters |
| 中文描述： | 1-CH 3-BIT DUAL-SLOPE ADC, PARALLEL ACCESS, PDIP40 |
| 封装： | PLASTIC, DIP-40 |
| 文件页数： | 8/21页 |
| 文件大小： | 209K |
| 代理商： | HI7131CPL |
3-1833
Definition of Specifications
Count
A Count is equal to one number change in the least signifi-
cant digit of the display. The analog size of a count referred
to ADC input is:
Max reading +1 for a 3
1
/
2
digit display is 2000 (1999+1).
Zero Input Reading
The reading of the ADC display when input voltage is zero
and there is no common mode voltage, i.e., the inputs are
shorted to COMMON pin.
Ratiometric Reading
The reading of the ADC display when input voltage is equal
to reference voltage, i.e., IN HI tied to REF HI and IN LO tied
to REF LO and COMMON pins. The accuracy of reference
voltage is not important for this test.
Rollover Error
Difference in the absolute value reading of ADC display for
equal magnitude but opposite polarity inputs. The input volt-
age should be close to full scale, which is the worst case
condition.
Linearity
Deviation of the ADC transfer function (output reading
versus input voltage transfer plot) from the best straight line
fitted to ADC transfer plot.
Scale Factor Temperature Coefficient
The rate of change of the slope of ADC transfer function due
to the change of temperature.
Equivalent Input Noise
The total random uncertainty of the ADC for converting a
fixed input value to an output reading. This uncertainty is
referred to input as a noise source which produces the
equivalent effect. It is given for zero input and is expressed
as Peak-to-Peak noise value and submultiples of Counts.
Overload Recovery Period
A measure of how fast the ADC will display an accurate
reading when input changes from an overload condition to a
value within the range. This is given as the number of con-
version cycles required after the input goes within the range.
Theory of Operation
The HI7131 and HI7133 are dual-slope integrating type A/D
converters. As the name implies, its output represents the
integral or average of the input signal. A basic block diagram
of a dual-slope integrating converter is shown in Figure 3. A
conventional conversion cycle has two distinct phases:
First, the input signal is integrated for a fixed interval of
time. This is called the signal integration phase. In this
phase, the input of the integrator is connected to the input
signal through the switch. During this time, charge builds
up on C
INT
, which is proportional to the input voltage.
The next phase is to discharge C
INT
. This is called reference
integration or deintegration phase, with the use of a fixed ref-
erence voltage. The time it takes to discharge the C
INT
is
directly proportional to the input signal. This time is con-
verted to a digital readout by means of a BCD counter,
driven by a clock oscillator. During this phase, the integrator
input is connected to an opposite polarity reference voltage
through the switch to discharge C
INT
.
Notice that during the integration phase, the rate of charge
built up on the capacitor is proportional to the level of the
input signal, and there is a fixed period of time to integrate
the input. However, during the discharge cycle the rate of
discharge is fixed and there is a variable time period for com-
plete discharge.
A 3
1
/
2
digit BCD counter is shown in the block diagram, the
period of integration is determined by 1000 counts of this
counter. Just prior to a measurement, the counter is reset to
zero and C
INT
has no charge. At the beginning of the mea-
surement, the control logic enables the counter and the inte-
grator input is connected to the input node. Charge begins
accumulating on C
INT
and the output of the integrator moves
down or up respectively for positive or negative inputs. This
process continues until the counter reaches 1000 counts.
This will signal the control logic for the start of the deintegrat-
ing cycle. The control logic resets the counter and connects
the integrator input to a reference voltage opposite to that of
the input signal. The charge accumulated on C
INT
is now
starting to be removed and the counter starts to count up
again. As soon as all the charge is removed, the output of
the integrator reaches 0V. This is detected by the compara-
tor and the control logic is signaled for the end of a measure-
ment cycle. At this time the number accumulated in the
counter is the representation of the input signal. This number
will be stored on the latches and displayed until the end of
the next measurement cycle.
Analog Count Size
1
+
---------------------------------------------
,
=
HI7131, HI7133
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|---|---|
| HI7133 | 制造商:INTERSIL 制造商全称:Intersil Corporation 功能描述:3 1/2 Digit, Low Power, High CMRR, LCD/LED Display-Type A/D Converters |
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