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参数资料
| 型号： | HI7133CPL |
| 厂商： | HARRIS SEMICONDUCTOR |
| 元件分类： | ADC |
| 英文描述： | Power Resistor; Series:200; Resistance:4.5kohm; Resistance Tolerance: 5%; Power Rating:8W; Resistor Element Material:Ceramic; Temperature Coefficient:260 ppm; Leaded Process Compatible:No; Packaging:Bulk RoHS Compliant: No |
| 中文描述： | DUAL-SLOPE ADC, PARALLEL ACCESS, PDIP40 |
| 文件页数： | 9/21页 |
| 文件大小： | 209K |
| 代理商： | HI7133CPL |
3-1834
Figure 3 shows a typical waveform of the integrator output
for 2 different positive input values and the associated repre-
sentation of the counter output for those inputs. T
INT
is the
time period of integrating phase. t
1
and t
2
are the end of
measurement for 2 different inputs.
The dual slope integrating technique puts the primary
responsibility for accuracy on the reference voltage. The val-
ues of R
INT
and C
INT
and the clock frequency (f
CLK
) are not
important, provided they are stable during each conversion
cycle. This can be expressed mathematically as follows:
It can be seen that the output reading of the ADC is only
proportional to the ratio of V
IN
over V
REF
. The last equation
also demonstrates that for the maximum display reading
(i.e., 1999) we will have V
IN
= 1.999 V
REF
. This implies that
in this configuration the full scale range of the converter is
twice its reference voltage.
The inherent advantages of integrating A/D converters are;
very small nonlinearity error, no possibility of missing codes
and good high frequency noise rejection.
Furthermore, the integrating converter has extremely high
normal mode rejection of frequencies whose periods are an
integral multiple of the integrating period (T
INT
). This feature
can be used to reject the line frequency related noises which
are riding on input voltage by appropriate selection of clock
frequency. This is shown in Figure 4.
V
IN
+V
REF
-V
REF
REFERENCE
VOLTAGE
3
1
/
2
DIGIT BCD COUNTER
MAXIMUM COUNT: 1999
RESET
ENABLE
CLK
CONTROL
LOGIC
CLOCK
GENERATOR
LATCHES
AND
DISPLAY DRIVERS
LATCH
DISPLAY
INTEGRATOR
COMPARATOR
f
CLK
R
INT
SWITCH
DRIVE
TIMING SIGNALS
-
+
-
+
C
INT
0
T
INT
t
1
t
2
t
t
COUNTER
OUTPUT
INTEGRATOR
OUTPUT
FOR POSITIVE
INPUT
VARIABLE
SLOPE
FIXED
SLOPE
VARIABLE
DEINTEGRATION
TIME
FIXED
INTEGRATION
TIME
1000
FIGURE 91. DUAL SLOPE INTEGRATING A/D CONVERTER
V
INT
INT
INT
---------------------------
V
IN
dt
0
TINT
∫
INT
INT
---------------------------
V
REF
dt
0
TDEINT
∫
=
=
V
INT
V
T
INT
INT
---------------------------
V
t
INT
INT
----------------------------------
=
=
V
IN
: Input Average Value During Integration Time
CLK
T
INT
1000
------------
=
t
DEINT
Accumulated Counts
CLK
------------
=
Accumulated Counts
1000
V
REF
--------------
Display Reading
=
=
30
20
10
0
0.1/T
INT
1/T
INT
10/T
INT
f
N
T
INT
= INTEGRATION PERIOD
f = INPUT OR NOISE FREQUENCY
FIGURE 92. NOISE REJECTION FOR INTEGRATING TYPE A/D
CONVERTER
HI7131, HI7133
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