参数资料
型号: HIP4082EVAL
厂商: Intersil
文件页数: 2/13页
文件大小: 0K
描述: EVAL BOARD FET DRIVER HIP4082
标准包装: 1
类型: FET 驱动器
适用于相关产品: HIP4082
所含物品: 完全组装的评估板
Application Note 9611
second inverter converts the 160V DC voltage into a quasi-
square-wave representation of a sin-wave having a
frequency of 55Hz with a peak voltage matching the high
voltage DC bus potential. A simple feed forward technique
regulates the AC secondary voltage to 115V AC while the
battery varies over a range of approximately 11V to 15V.
(Through component modification, 230VAC is possible.)
The aforementioned features are similar to those of at least
one commercially available battery inverter (Radio Shack,
Catalog number 22-132A). Thermal limiting on the
evaluation unit is approximately 120W at ambient
temperatures to 30 o C (a little lower than the competitive unit)
in order to allow the unit to be operated without a heat-
sinking enclosure. This allows users to probe various points
in order to provide a better understanding of circuit
operation.
Primary Inverter Design
Input Filter
The primary-side inverter is comprised of a simple R-C input
filter. Capacitors, C 5 and C 6 provide a stiff, sag-free source
Choosing Proper Dead-Time
The dead-time chosen for eliminating shoot-through currents
in the Q 1 -Q 4 and Q 2 -Q 3 MOSFET pairs is determined by the
value of R 2 connected between the DEL and V SS pins of the
HIP4082. The 15K value chosen provides approximately
0.5s of dead-time, sufficient to avoid shoot-through when
using RFP70N06 MOSFETs. Refer to the HIP4082 data
sheet, File Number 3676, Figure 16 for dead-time versus
delay resistance characteristics.
C2 (MAX)
9V
C1 FREQ.
118.28kHz
1
2
for the inverter bridge comprised of Q 1 through Q 4 as shown
in the schematic (see Appendix). To aid this process,
CH1 = 5V
CH2 = 5V
M = 2.5 μ s CH1
4.2V
Resistor, R 37 and ceramic, non-inductive capacitor, C 7 ,
parallel C 5 and C 6 . Automotive applications can be fraught
with voltage transients across the battery terminals. To
prevent these transients from exceeding the V CC voltage
ratings of the HIP4082 and other ICs on the primary inverter
section, R 7 , C 4 and D 3 clamp the V CC voltage to 16V or
less.
FIGURE 1. 555 TIMER WAVEFORMS
C2 (MAX)
13.8V
Primary Inverter Waveform Generation
To minimize the size of the secondary filter, a 50% duty cycle
square-wave was chosen for primary excitation. With a
nearly constant, low-ripple voltage, secondary filtering can
be minimized and ripple nearly eliminated. An inexpensive
Intersil ICM7555 timer was chosen. This timer, an improved
555 timer, reduces V CC to ground cross conduction current
spikes, thereby minimizing bias current requirements.
1
2
C1 FREQ.
59.544kHz
LOW
SIGNAL
AMPL.
The timer, U 1 , operates in the astable mode, accomplished
by tying pins 2 and 6 of the timer together. The astable mode
CH1 = 10V
CH2 = 10V
M = 2.5 μ s CH1
4.2V
requires only one resistor, R 1 , and one capacitor, C 3 . A 50%
duty-cycle square-wave is available at the “OUT” (pin 3)
terminal of timer, U 1 , as shown in Figure 1.
The timer ‘out’ pin drives the clock input, pin 3, of a CA4013
D-flip-flop connected as a divide by two circuit. To
accomplish the divide-by-two function, the QNOT output of
the flip-flop is fed back to its own data, D, input. The Q and
QNOT outputs of the CA4013 provide an exact 50% duty-
cycle square-wave at half the timer’s output frequency and
are applied to the ALI-BHI and the AHI-BLI gate control
inputs of the HIP4082 respectively as shown in Figure 2. The
ICM7555 clock frequency was chosen to be 120kHz so that
the primary inverter frequency would be 60kHz.
2
FIGURE 2. INPUT WAVEFORMS TO THE HIP4082
Controlling di/dt and Switching Losses
Choice of gate resistor values for R 3 -R 5 , and R 8 is based
upon several factors. The gate resistors tailor the turn-on and
turn-off rise times of the power MOSFETs and the
commutating di/dt. The di/dt affects commutation losses and
body diode recovery losses. As di/dt increases, recovery
losses increase, but the commutation losses decrease. As
di/dt decreases, recovery losses decrease, and commutation
losses increase. Generally there is an ideal commutation di/dt
which minimizes the sum of these switching losses.
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