参数资料
型号: HIP4086APZ
厂商: Intersil
文件页数: 16/16页
文件大小: 0K
描述: IC DRIVER FET 3PHASE N-CH 24DIP
产品培训模块: Solutions for Industrial Control Applications
标准包装: 15
配置: 3 相桥
输入类型: 反相和非反相
延迟时间: 65ns
电流 - 峰: 500mA
配置数: 1
输出数: 3
高端电压 - 最大(自引导启动): 95V
电源电压: 7 V ~ 15 V
工作温度: -40°C ~ 125°C
安装类型: 通孔
封装/外壳: 24-DIP(0.300",7.62mm)
供应商设备封装: 24-PDIP
包装: 管件
产品目录页面: 1239 (CN2011-ZH PDF)
HIP4086, HIP4086A
Package Outline Drawing
M24.3
24 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE (SOIC)
Rev 2, 3/11
24
INDEX
AREA
7.60 (0.299 )
7.40 (0.291) 10.65 (0.419 )
10.00 (0.394)
DETAIL "A "
1
2
3
TOP VIEW
15.60 (0.614 )
15.20 (0.598)
SEATING PLANE
2.65 (0.104)
2.35 (0.093)
1.27 (0.050)
0.40 (0.016)
0.75 (0.029)
0.25 (0.010)
x 45°
1.27 (0.050)
0.51 (0.020)
0.33 (0.013)
0.30 (0.012)
0.10 (0.004)
8 °
0.32 (0.012)
0.23 (0.009)
SIDE VIEW “A
SIDE VIEW “B”
1.981 (0.078)
NOTES:
1. Dimensioning and tolerancing per ANSI Y14.5M-1982.
2. Package length does not include mold flash, protrusions or gate
burrs. Mold flash, protrusion and gate burrs shall not exceed
0.15mm (0.006 inch) per side.
3. Package width does not include interlead flash or protrusions.
Interlead flash and protrusions shall not exceed 0.25mm
(0.010 inch) per side.
9.373 (0.369)
4. The chamfer on the body is optional. If it is not present, a visual
index feature must be located within the crosshatched area.
5. Terminal numbers are shown for reference only.
6. The lead width as measured 0.36mm (0.014 inch) or greater above
the seating plane, shall not exceed a maximum value of 0.61mm
(0.024 inch).
7. Controlling dimension: MILLIMETER. Converted inch dimensions in
( ) are not necessarily exact.
8. This outline conforms to JEDEC publication MS-013-AD ISSUE C.
1.27 (0.050)
0.533 (0.021)
TYPICAL RECOMMENDED LAND PATTERN
16
FN4220.9
February 1, 2013
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