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参数资料
| 型号： | HIP5060DW |
| 厂商： | INTERSIL CORP |
| 元件分类： | 稳压器 |
| 英文描述： | Power Control IC Single Chip PowerSupply |
| 中文描述： | 20 A SWITCHING REGULATOR, 1100 kHz SWITCHING FREQ-MAX, UUC37 |
| 封装： | WAFER |
| 文件页数： | 3/6页 |
| 文件大小： | 615K |
| 代理商： | HIP5060DW |
3
Absolute Maximum Ratings
Thermal Information
DC Supply Voltage, V+. . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 45V
DMOS Drain Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 60V
DMOS Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20A
DC Logic Supply. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 16V
Output Voltage, Logic Outputs . . . . . . . . . . . . . . . . . . . -0.3V to 16V
Input Voltage, Analog and Logic. . . . . . . . . . . . . . . . . . -0.3V to 16V
Operating Junction Temperature Range . . . . . . . . . .0
o
C to +110
o
C
Storage Temperature Range . . . . . . . . . . . . . . . . . -55
o
C to +150
o
C
Thermal Resistance
(Solder Mounted to . . . . . . . . . . . . . . . . . . . . . . . . . 3
o
C/W Max
0.050” Thick Copper Heat Sink)
Maximum Junction Temperature. . . . . . . . . . . . . . . . . . . . . . +110
o
C
(Controlled By Thermal Shutdown Circuit)
θ
JC
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
Electrical Specifications
V+ = 36V, T
J
= 0
o
C to +110
o
C; Unless Otherwise Specified
SYMBOL
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
DEVICE PARAMETERS
I+
Supply Current
PSEN = 12V
-
19.5
32
mA
V
DDA
Internal Regulator Output
Voltage
V+ = 15V to 45V, I
OUT
= 10mA
11.0
-
13.2
V
VINP
Reference Voltage
I
VINP
= 0mA
5.01
5.1
5.19
V
R
VINP
VINP Resistance
VINP = 0
-
900
-
ERROR AMPLIFIERS
|V
IO
|
Input Offset Voltage
(VREG - VINP)
I
VCMP
= 0mA
-
-
10
mV
R
IN
VREG
Input Resistance to GND
VREG = 5.1V
-
56
-
k
g
m
(VREG)
VREG Transconductance
I
VCMP
/(VREG - VINP)
VCMP = 1V to 8V, SFST = 11V
15
30
50
mS
g
m
(SFST)
SFST Transconductance
I
VCMP
/(VREG - SFST)
V
SFST
< 4.9V
0.8
-
6
mS
I
VCMP
Maximum Source Current
VREG = 4.95V, VCMP = 8V
-2.5
-
-0.75
mA
I
VCMP
Maximum Sink Current
VREG = 5.25V, VCMP = 0.4V
0.75
-
2.5
mA
OVTH
Over-Voltage Threshold
Voltage at VREG for FLTN to be
latched
6.2
-
6.7
V
CLOCK
fq
Internal Clock Frequency
SLCT = 0V, V
DDD
= 12V
0.9
1.0
1.1
MHz
V
TH
CKIN
External Clock Input Threshold
Voltages
SLCT = 12V
33
-
66
%V
DDD
DMOS TRANSISTORS
r
DS(on)
Drain-Source On-State
Resistance
I Drain = 5A, T
J
= +25
o
C
-
-
0.13
I
DSS
Drain-Source Leakage Current
Drain to Source Voltage = 60V
-
1
100
μ
A
CURRENT CONTROLLED PWM
|V
IO
| VCMP
Buffer Offset Voltage (VCMP -
V
IRFO
)
IRFO = 0mA to -5mA,
VCMP = 0.2V to 7.6V
-
-
125
mV
V
TH
IRFO
Voltage at IRFO that disables
PWM. This is due to low load
current
100
-
270
mV
HIP5060
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