参数资料
型号: HIP6012CBZ-T
厂商: Intersil
文件页数: 9/12页
文件大小: 0K
描述: IC CTRLR PWM BUCK SYNC 14-SOIC
标准包装: 1
应用: 控制器,Intel Pentium? Pro、PowerP、Alpha
输入电压: 5V,12V
输出数: 1
输出电压: 1.3 V ~ 12 V
工作温度: 0°C ~ 70°C
安装类型: *
封装/外壳: 14-SOIC(0.154",3.90mm 宽)
供应商设备封装: *
包装: 标准包装
产品目录页面: 1242 (CN2011-ZH PDF)
其它名称: HIP6012CBZ-TDKR
HIP6012
These equations assume linear voltage-current transitions
and do not adequately model power loss due the reverse-
recovery of the lower MOSFETs body diode. The
gate-charge losses are dissipated by the HIP6012 and don't
heat the MOSFETs. However, large gate-charge increases
the switching interval, t SW which increases the upper
MOSFET switching losses. Ensure that both MOSFETs are
within their maximum junction temperature at high ambient
temperature by calculating the temperature rise according to
package thermal-resistance specifications. A separate
heatsink may be necessary depending upon MOSFET
power, package type, ambient temperature and air flow.
Standard-gate MOSFETs are normally recommended for
use with the HIP6012. However, logic-level gate MOSFETs
Figure 10 shows the upper gate drive supplied by a direct
connection to V CC . This option should only be used in
converter systems where the main input voltage is +5 VDC
or less. The peak upper gate-to-source voltage is
approximately VCC less the input supply. For +5V main
power and +12 VDC for the bias, the gate-to-source voltage
of Q1 is 7V. A logic-level MOSFET is a good choice for Q1
and a logic-level MOSFET can be used for Q2 if its absolute
gate-to-source voltage rating exceeds the maximum voltage
applied to PVCC.
+12V
+5V OR LESS
VCC
can be used under special circumstances. The input voltage,
upper gate drive level, and the MOSFETs absolute gate-to-
HIP6012
BOOT
source voltage rating determine whether logic-level
MOSFETs are appropriate.
Figure 9 shows the upper gate drive (BOOT pin) supplied by
a bootstrap circuit from V CC . The boot capacitor, C BOOT
UGATE
PHASE
+5V
OR +12V
PVCC
Q1
NOTE:
V G-S ≈ V CC - 5V
develops a floating supply voltage referenced to the PHASE
pin. This supply is refreshed each cycle to a voltage of V CC
less the boot diode drop (V D ) when the lower MOSFET, Q2
-
+
LGATE
PGND
Q2
D2
NOTE:
V G-S ≈ PVCC
turns on. A logic-level MOSFET can only be used for Q1 if
the MOSFETs absolute gate-to-source voltage rating
exceeds the maximum voltage applied to V CC . For Q2, a
logic-level MOSFET can be used if its absolute gate-to-
source voltage rating exceeds the maximum voltage applied
to PVCC.
GND
FIGURE 10. UPPER GATE DRIVE - DIRECT V CC DRIVE OPTION
Schottky Selection
+12V
D BOOT
Rectifier D2 is a clamp that catches the negative inductor
swing during the dead time between turning off the lower
VCC
+
VO
-
+5V OR +12V
MOSFET and turning on the upper MOSFET. The diode must
be a Schottky type to prevent the lossy parasitic MOSFET
body diode from conducting. It is acceptable to omit the diode
HIP6012
BOOT
UGATE
PHASE
C BOOT
Q1
NOTE:
V G-S ≈ V CC - V D
and let the body diode of the lower MOSFET clamp the
negative inductor swing, but efficiency will drop one or two
percent as a result. The diode's rated reverse breakdown
voltage must be greater than the maximum input voltage.
+5V
PVCC OR +12V
-
+
LGATE
PGND
Q2
D2
NOTE:
V G-S ≈ PVCC
GND
FIGURE 9. UPPER GATE DRIVE - BOOTSTRAP OPTION
9
FN4324.2
December 27, 2004
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