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参数资料
| 型号： | HIP6017EVAL1 |
| 厂商： | Intersil Corporation |
| 元件分类： | 基准电压源/电流源 |
| 英文描述： | Advanced PWM and Dual Linear Power Control |
| 中文描述： | 先进的双PWM和线性功率控制 |
| 文件页数： | 11/14页 |
| 文件大小： | 135K |
| 代理商： | HIP6017EVAL1 |
2-220
The modulator transfer function is the small-signal transfer
function of V
OUT
/V
E/A
. This function is dominated by a DC
gain and the output filter, with a double pole break frequency
at F
LC
and a zero at F
ESR
. The DC gain of the modulator is
simply the input voltage, V
IN
, divided by the peak-to-peak
oscillator voltage,
V
OSC
.
Modulator Break Frequency Equations
The compensation network consists of the error amplifier
internal to the HIP6017 and the impedance networks Z
IN
and Z
FB
. The goal of the compensation network is to
provide a closed loop transfer function with an acceptable
0dB crossing frequency (f
0dB
) and adequate phase margin.
Phase margin is the difference between the closed loop
phase at f
0dB
and 180 degrees
.
The equations below relate
the compensation network’s poles, zeros and gain to the
components (R1, R2, R3, C1, C2, and C3) in Figure 11.
Use these guidelines for locating the poles and zeros of the
compensation network:
1. Pick Gain (R2/R1) for desired converter bandwidth
2. Place 1
ST
Zero Below Filter’s Double Pole (~75% F
LC
)
3. Place 2
ND
Zero at Filter’s Double Pole
4. Place 1
ST
Pole at the ESR Zero
5. Place 2
ND
Pole at Half the Switching Frequency
6. Check Gain against Error Amplifier’s Open-Loop Gain
7. Estimate Phase Margin - Repeat if Necessary
Compensation Break Frequency Equations
Figure 12 shows an asymptotic plot of the DC-DC
converter’s gain vs frequency. The actual modulator gain has
a peak due to the high Q factor of the output filter at F
LC
,
which is not shown in Figure 12. Using the above guidelines
should yield a compensation gain similar to the curve
plotted. The open loop error amplifier gain bounds the
compensation gain. Check the compensation gain at F
P2
with the capabilities of the error amplifier. The closed loop
gain is constructed on the log-log graph of Figure 12 by
adding the modulator gain (in dB) to the compensation gain
(in dB). This is equivalent to multiplying the modulator
transfer function to the compensation transfer function and
plotting the gain.
The compensation gain uses external impedance networks
Z
FB
and Z
IN
to provide a stable, high bandwidth loop. A
stable control loop has a 0dB gain crossing with
-20dB/decade slope and a phase margin greater than 45
degrees. Include worst case component variations when
determining phase margin.
Component Selection Guidelines
Output Capacitor Selection
The output capacitors for each output have unique
requirements. In general the output capacitors should be
selected to meet the dynamic regulation requirements.
Additionally, the PWM converters require an output capacitor
to filter the current ripple. The linear regulator is internally
compensated and requires an output capacitor that meets
the stability requirements. The load transient for the
microprocessor core requires high quality capacitors to
supply the high slew rate (di/dt) current demands.
PWM Output Capacitors
Modern microprocessors produce transient load rates above
10A/ns. High frequency capacitors initially supply the
transient and slow the current load rate seen by the bulk
capacitors. The bulk filter capacitor values are generally
determined by the ESR (effective series resistance) and ESL
(effective series inductance) parameters rather than actual
capacitance.
High frequency decoupling capacitors should be placed as
close to the power pins of the load as physically possible. Be
careful not to add inductance in the circuit board wiring that
could cancel the usefulness of these low inductance
components. Consult with the manufacturer of the load on
specific decoupling requirements.
Use only specialized low-ESR capacitors intended for
switching regulator applications for the bulk capacitors. The
bulk capacitor’s ESR determines the output ripple voltage
and the initial voltage drop after a high slew-rate transient.
An aluminum electrolytic capacitor’s ESR value is related to
F
LC
L
O
2
π
C
O
×
×
---------------------------------------
=
F
ESR
O
-----------------------------------------
=
F
Z1
-----------------------------------
=
F
Z2
R3
)
C3
×
------------------------+
=
F
P1
2
π
R
2
--------+
×
×
------------------------------------------------------
=
F
P2
-----------------------------------
=
100
80
60
40
20
0
-20
-40
-60
F
P1
F
Z2
10M
1M
100K
10K
1K
100
10
OPEN LOOP
ERROR AMP GAIN
F
Z1
F
P2
20LOG
(R
2
/R
1
)
F
LC
F
ESR
COMPENSATION
GAIN
G
FREQUENCY (Hz)
20LOG
(V
IN
/
V
OSC
)
MODULATOR
GAIN
FIGURE 12. ASYMPTOTIC BODE PLOT OF CONVERTER GAIN
CLOSED LOOP
GAIN
HIP6017
相关PDF资料 |
PDF描述 |
|---|---|
| HIP6017 | Advanced PWM and Dual Linear Power Control |
| HIP6017CB | Advanced PWM and Dual Linear Power Control |
| HIP6018EVAL1 | Advanced PWM and Dual Linear Power Control |
| HIP6018 | FPGA - 100000 SYSTEM GATE 2.5 VOLT - NOT RECOMMENDED for NEW DESIGN |
| HIP6018CB | Advanced PWM and Dual Linear Power Control |
相关代理商/技术参数 |
参数描述 |
|---|---|
| HIP6018 | 制造商:INTERSIL 制造商全称:Intersil Corporation 功能描述:Advanced PWM and Dual Linear Power Control |
| HIP6018B | 制造商:INTERSIL 制造商全称:Intersil Corporation 功能描述:Advanced PWM and Dual Linear Power Control |
| HIP6018B_05 | 制造商:INTERSIL 制造商全称:Intersil Corporation 功能描述:Advanced PWM and Dual Linear Power Control |
| HIP6018BCB | 功能描述:IC REG TRPL BCK/LINEAR 24-SOIC RoHS:否 类别:集成电路 (IC) >> PMIC - 稳压器 - 线性 + 切换式 系列:- 标准包装:2,500 系列:- 拓扑:降压（降压）同步（3），线性（LDO）（2） 功能:任何功能 输出数:5 频率 - 开关:300kHz 电压/电流 - 输出 1:控制器 电压/电流 - 输出 2:控制器 电压/电流 - 输出 3:控制器 带 LED 驱动器:无 带监控器:无 带序列发生器:是 电源电压:5.6 V ~ 24 V 工作温度:-40°C ~ 85°C 安装类型:* 封装/外壳:* 供应商设备封装:* 包装:* |
| HIP6018BCB-T | 功能描述:IC REG TRPL BCK/LINEAR 24-SOIC RoHS:否 类别:集成电路 (IC) >> PMIC - 稳压器 - 线性 + 切换式 系列:- 标准包装:2,500 系列:- 拓扑:降压（降压）同步（3），线性（LDO）（2） 功能:任何功能 输出数:5 频率 - 开关:300kHz 电压/电流 - 输出 1:控制器 电压/电流 - 输出 2:控制器 电压/电流 - 输出 3:控制器 带 LED 驱动器:无 带监控器:无 带序列发生器:是 电源电压:5.6 V ~ 24 V 工作温度:-40°C ~ 85°C 安装类型:* 封装/外壳:* 供应商设备封装:* 包装:* |
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