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参数资料
| 型号： | HIP6020CB |
| 厂商： | HARRIS SEMICONDUCTOR |
| 元件分类： | 稳压器 |
| 英文描述： | Advanced Dual PWM and Dual Linear Power Controller |
| 中文描述： | DUAL SWITCHING CONTROLLER, 1000 kHz SWITCHING FREQ-MAX, PDSO28 |
| 封装： | SOIC-28 |
| 文件页数： | 8/15页 |
| 文件大小： | 139K |
| 代理商： | HIP6020CB |
2-288
Figure 7 shows a simplified schematic of the fault logic. An
over-voltage detected on VSEN1 immediately sets the fault
latch. A sequence of three over-current fault signals also
sets the fault latch. The over-current latch is set dependent
upon the states of the over-current (OC1 and OC2), linear
under-voltage (LUV) and the soft-start signals. A window
comparator monitors the SS pin and indicates when C
SS
is
fully charged to 4.5V (UP signal). An under-voltage on either
linear output (VSEN3 and VSEN4) is ignored until after the
soft-start interval (T4 in Figure 6). This allows V
OUT3
and
V
OUT4
to increase without fault at start-up. Cycling the bias
input voltage (+12V
IN
on the VCC pin off then on) resets the
counter and the fault latch.
Over-Voltage Protection
During operation, a short across the synchronous PWM
upper MOSFET (Q1) causes V
OUT1
to increase. When the
output exceeds the over-voltage threshold of 115% of
DACOUT, the over-voltage comparator trips to set the fault
latch and turns the lower MOSFET (Q2) on. This blows the
input fuse and reduces V
OUT1
. The fault latch raises the
FAULT/RT pin to VCC.
A separate over-voltage circuit provides protection during
the initial application of power. For voltages on the VCC pin
below the power-on reset (and above ~4V), the output level
is monitored for voltages above 1.3V. Should VSEN1 exceed
this level, the lower MOSFET, Q2 is driven on.
Over-Current Protection
All outputs are protected against excessive over-currents.
Both PWM controllers use the upper MOSFET’s on-
resistance, r
DS(ON)
to monitor the current for protection
against shorted outputs. Both linear regulators monitor their
respective VSEN pins for under-voltage to protect against
excessive currents.
Figure 8 illustrates the over-current protection with an
overload on OUT2. The overload is applied at T0 and the
current increases through the inductor (L
OUT2
). At time T1,
the OVER-CURRENT2 comparator trips when the voltage
across Q3 (i
D
r
DS(ON)
) exceeds the level programmed by
R
OCSET
. This inhibits all outputs, discharges the soft-start
capacitor (C
SS
) with a 28
μ
A current sink, and increments the
counter. C
SS
recharges at T2 and initiates a soft-start cycle
with the error amplifiers clamped by soft-start. With OUT2 still
overloaded, the inductor current increases to trip the over-
current comparator. Again, this inhibits all outputs, but the
soft-start voltage continues increasing to 4.5V before
discharging. The counter increments to 2. The soft-start cycle
repeats at T3 and trips the over-current comparator. The SS
pin voltage increases to 4.5V at T4 and the counter
increments to 3. This sets the fault latch to disable the
converter. The fault is reported on the FAULT/RT pin.
The PWM1 controller operates in the same way as PWM2 to
over-current faults. Additionally, the two linear controllers
monitor the VSEN pins for an under-voltage. Should
excessive currents cause VSEN3 or VSEN4 to fall below the
linear under-voltage threshold, the LUV signal sets the over-
current latch, providing C
SS
isfully charged. Blanking the LUV
signal during the C
SS
charge interval allows the linear
outputs to build above the under-voltage threshold during
normal operation. Cycling the bias input power off then on
resets the counter and the fault latch.
Resistors (R
OCSET1
and R
OCSET2
) program the over-current
trip levels for each PWM converter. As shown in Figure 9, the
internal200
μ
Acurrentsink(I
OCSET
)developsavoltageacross
R
OCSET
(V
SET
) that is referenced to V
IN
. The DRIVE signal
enables the over-current comparator (OVER-CURRENT1 or
OVER-CURRENT2). When the voltage across the upper
MOSFET (V
DS(ON)
) exceeds V
SET
, the over-current
comparator trips to set the over-current latch. Both V
SET
and
V
DS
are referenced to V
IN
and a small capacitor across
R
OCSET
helps V
OCSET
track the variations of V
IN
due to
FIGURE 5. OVER-CURRENT OPERATION
S
0A
0V
2V
4V
TIME
T1
T2
T3
T0
T4
F
0V
10V
OVERLOAD
APPLIED
FAULT
REPORTED
COUNT
= 1
COUNT
= 2
COUNT
= 3
FIGURE 6. OVER-CURRENT DETECTION
UGATE
OCSET
PHASE
OVER-
CURRENT
+
-
GATE
CONTROL
VCC
OC
200
μ
A
V
DS
i
D
V
SET
R
OCSET
V
IN
= +5V
OVER-CURRENT TRIP:
VDS
I
OCSET
+
+
PWM
DRIVE
iD
rDS ON
)
×
IOCSET
ROCSET
×
>
VSET
>
VPHASE
VOCSET
VIN
VIN
VDS
VSET
–
=
–
=
HIP6020
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相关代理商/技术参数 |
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|---|---|
| HIP6020CB-T | 制造商:Rochester Electronics LLC 功能描述:DUAL PWM AND 2 LINEAR CONTROLLER TAPE AND REEL - Tape and Reel |
| HIP6020EVAL1 | 制造商:INTERSIL 制造商全称:Intersil Corporation 功能描述:Advanced Dual PWM and Dual Linear Power Controller |
| HIP6021 | 制造商:INTERSIL 制造商全称:Intersil Corporation 功能描述:Advanced PWM and Triple Linear Power Controller |
| HIP6021_05 | 制造商:INTERSIL 制造商全称:Intersil Corporation 功能描述:Advanced PWM and Triple Linear Power Controller |
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