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| 型号： | HIP6021CBZ-T |
| 厂商： | Intersil |
| 文件页数： | 11/15页 |
| 文件大小： | 408K |
| 描述： | IC REG QD BCK/LINEAR 28-SOIC |
| 标准包装： | 1,000 |
| 拓扑： | 降压（降压）同步（1），线性（LDO）（3） |
| 功能： | 任何功能 |
| 输出数： | 4 |
| 频率 - 开关： | 215kHz |
| 电压/电流 - 输出 1： | 控制器 |
| 电压/电流 - 输出 2： | 控制器 |
| 电压/电流 - 输出 3： | 控制器 |
| 带 LED 驱动器： | 无 |
| 带监控器： | 无 |
| 带序列发生器： | 无 |
| 电源电压： | 5 V ~ 12 V |
| 工作温度： | 0°C ~ 70°C |
| 安装类型： | * |
| 封装/外壳： | 28-SOIC（0.295"，7.50mm 宽） |
| 供应商设备封装： | * |
| 包装： | 带卷 (TR) |
11
Layout Considerations
MOSFETs switch very fast and efficiently. The speed with
which the current transitions from one device to another
causes voltage spikes across the interconnecting
impedances and parasitic circuit elements. The voltage
spikes can degrade efficiency, radiate noise into the circuit,
and lead to device over-voltage stress. Careful component
layout and printed circuit design minimizes the voltage
spikes in the converter. Consider, as an example, the turn-
off transition of the upper PWM MOSFET. Prior to turn-off,
the upper MOSFET was carrying the full load current.
During the turn-off, current stops flowing in the upper
MOSFET and is picked up by the lower MOSFET or
Schottky diode. Any inductance in the switched current
path generates a large voltage spike during the switching
interval. Careful component selection, tight layout of the
critical components, and short, wide circuit traces minimize
the magnitude of voltage spikes. See the Application Note
ANTBD for evaluation board drawings of the component
placement and printed circuit board.
There are two sets of critical components in a DC-DC
converter using a HIP6020 controller. The switching power
components are the most critical because they switch large
amounts of energy, and as such, they tend to generate
equally large amounts of noise. The critical small signal
components are those connected to sensitive nodes or
those supplying critical bypass current.
The power components and the controller IC should be
placed first. Locate the input capacitors, especially the high-
frequency ceramic decoupling capacitors, close to the power
switches. Locate the output inductor and output capacitors
between the MOSFETs and the load. Locate the PWM
controller close to the MOSFETs.
The critical small signal components include the bypass
capacitor for VCC and the soft-start capacitor, C
SS
. Locate
these components close to their connecting pins on the
control IC. Minimize any leakage current paths from SS
node, since the internal current source is only 28礎.
A multi-layer printed circuit board is recommended. Figure
8shows the connections of the critical components in the
converter. Note that the capacitors C
IN
and C
OUT
each
represent numerous physical capacitors. Dedicate one
solid layer for a ground plane and make all critical
component ground connections with vias to this layer.
Dedicate another solid layer as a power plane and break
this plane into smaller islands of common voltage levels.
The power plane should support the input power and
output power nodes. Use copper filled polygons on the top
and bottom circuit layers for the PHASE nodes, but do not
unnecessarily oversize these particular islands. Since the
PHASE nodes are subjected to very high dV/dt voltages,
the stray capacitor formed between these islands and the
surrounding circuitry will tend to couple switching noise.
Use the remaining printed circuit layers for small signal
wiring. The wiring traces from the control IC to the
MOSFET gate and source should be sized to carry 2A peak
currents.
PWM Controller Feedback Compensation
The PWM controller uses voltage-mode control for output
regulation. This section highlights the design consideration
for a PWM voltage-mode controller. Apply the methods and
considerations only to the PWM controller.
Figure 9 highlights the voltage-mode control loop for a
synchronous-rectified buck converter. The output voltage
(V
OUT
) is regulated to the Reference voltage level. The
reference voltage level is the DAC output voltage (DACOUT).
The error amplifier (Error Amp) output (V
E/A
) is compared
with the oscillator (OSC) triangular wave to provide a pulse-
width modulated (PWM) wave with an amplitude of V
IN
at
the PHASE node. The PWM wave is smoothed by the output
filter (L
O
and C
O
).
The modulator transfer function is the small-signal transfer
function of V
OUT
/V
E/A
. This function is dominated by a DC
Gain, given by V
IN
/V
OSC
, and shaped by the output filter,
with a double pole break frequency at F
LC
and a zero at
F
ESR
.
Modulator Break Frequency Equations
The compensation network consists of the error amplifier
(internal to the HIP6021) and the impedance networks Z
IN
and Z
FB
. The goal of the compensation network is to provide
a closed loop transfer function with high 0dB crossing
frequency (f
0dB
) and adequate phase margin. Phase margin
is the difference between the closed loop phase at f
0dB
and
180 degrees. The equations below relate the compensation
networks poles, zeros and gain to the components (R1, R2,
R3, C1, C2, and C3) in Figure 8. Use these guidelines for
locating the poles and zeros of the compensation network:
1. Pick Gain (R2/R1) for desired converter bandwidth
2. Place 1
ST
Zero Below Filters Double Pole (~75% F
LC
)
3. Place 2
ND
Zero at Filters Double Pole
4. Place 1
ST
Pole at the ESR Zero
5. Place 2
ND
Pole at Half the Switching Frequency
6. Check Gain against Error Amplifiers Open-Loop Gain
7. Estimate Phase Margin - Repeat if Necessary
F
LC
1
2?/DIV>
L
O
C
O
?/DIV>
?/DIV>
--------------------------------------- -
=
F
ESR
1
2?nbsp ESR C
O
?/DIV>
?/DIV>
---------------------------------------- -
=
HIP6021
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相关代理商/技术参数 |
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|---|---|
| HIP6021EVAL1 | 功能描述:电源管理IC开发工具 HIP6021 EVAL BRD RoHS:否 制造商:Maxim Integrated 产品:Evaluation Kits 类型:Battery Management 工具用于评估:MAX17710GB 输入电压: 输出电压:1.8 V |
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