参数资料
型号: HIP6302CBZA-T
厂商: Intersil
文件页数: 9/16页
文件大小: 0K
描述: IC REG CTRLR BUCK PWM 16-SOIC
标准包装: 2,500
PWM 型: 控制器
输出数: 2
频率 - 最大: 305kHz
电源电压: 4.75 V ~ 5.25 V
降压:
升压:
回扫:
反相:
倍增器:
除法器:
Cuk:
隔离:
工作温度: 0°C ~ 70°C
封装/外壳: 16-SOIC(0.154",3.90mm 宽)
包装: 带卷 (TR)
HIP6302
Figure 5 shows the regulator operating from an ATX supply.
In this figure, note the slight rise in PGOOD as the 5V supply
rises.The PGOOD output stage is made up of NMOS and
PMOS transistors. On the rising V CC , the PMOS device
becomes active slightly before the NMOS transistor pulls
“down”, generating the slight rise in the PGOOD voltage.
Note that Figure 5 shows the 12V gate driver voltage
available before the 5V supply to the HIP6302 has reached
its threshold level. If conditions were reversed and the 5V
supply was to rise first, the start-up sequence would be
different. In this case the HIP6303 will sense an over-current
condition due to charging the output capacitors. The supply
.
12V ATX
SUPPLY
PGOOD
V CORE
5 V ATX
SUPPLY
will then restart and go through the normal Soft-Start cycle.
V IN = 5V, CORE LOAD CURRENT = 31A
FREQUENCY 200kHz
PWM 1
OUTPUT
ATX SUPPLY ACTIVATED BY ATX “PS-ON PIN”
FIGURE 5. SUPPLY POWERED BY ATX SUPPLY
DELAY TIME
PGOOD
V CORE
5V
V CC
Fault Protection
The HIP6302 protects the microprocessor and the entire
power system from damaging stress levels. Within the
HIP6302 both Over-Voltage and Over-Current circuits are
incorporated to protect the load and regulator.
Over-Voltage
The VSEN pin is connected to the microprocessor CORE
voltage. A CORE over-voltage condition is detected when
the VSEN pin goes more than 15% above the programmed
V IN = 12V
FIGURE 3. START-UP OF 4 PHASE SYSTEM OPERATING AT
500kHz
V COMP
DELAY TIME
PGOOD
V CORE
5V
V CC
V IN = 12V
FIGURE 4. START-UP OF 4 PHASE SYSTEM OPERATING AT
200kHz
9
VID level.
The over-voltage condition is latched, disabling normal PWM
operation, and causing PGOOD to go low. The latch can
only be reset by lowering and returning V CC high to initiate a
POR and Soft-Start sequence.
During a latched over-voltage, the PWM outputs will be
driven either low or three state, depending upon the VSEN
input. PWM outputs are driven low when the VSEN pin
detects that the CORE voltage is 15% above the
programmed VID level. This condition drives the PWM
outputs low, resulting in the lower or synchronous rectifier
MOSFETs to conduct and shunt the CORE voltage to
ground to protect the load.
If after this event, the CORE voltage falls below the over-
voltage limit (plus some hysteresis), the PWM outputs will
three state. The HIP6601 family drivers pass the three state
information along, and shuts off both upper and lower
MOSFETs. This prevents “dumping” of the output capacitors
back through the lower MOSFETS, avoiding a possibly
destructive ringing of the capacitors and output inductors. If
the conditions that caused the over-voltage still persist, the
PWM outputs will be cycled between three state and V CORE
clamped to ground, as a hysteretic shunt regulator.
FN4766.3
December 27, 2004
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