参数资料
型号: HIP6303CB
厂商: Intersil
文件页数: 12/17页
文件大小: 0K
描述: IC REG CTRLR BUCK PWM 20-SOIC
标准包装: 38
PWM 型: 控制器
输出数: 4
频率 - 最大: 350kHz
电源电压: 4.75 V ~ 5.25 V
降压:
升压:
回扫:
反相:
倍增器:
除法器:
Cuk:
隔离:
工作温度: 0°C ~ 70°C
封装/外壳: 20-SOIC(0.295",7.50mm 宽)
包装: 管件
HIP6303
Droop, Selection of R IN
The average of the currents detected through the R ISEN
resistors is also steered to the FB pin. There is no DC return
path connected to the FB pin except for R IN , so the average
current creates a voltage drop across R IN . This drop
increases the apparent V CORE voltage with increasing load
current, causing the system to decrease V CORE to maintain
balance at the FB pin. This is the desired “droop” voltage
inductors, the switching frequency of each channel, and the
values of the input and output voltage. Ignoring secondary
effects, such as series resistance, the peak to peak value of
the sawtooth current can be described by:
i PK-PK = (V IN x V CORE - V CORE2 ) / (L x F SW x V IN )
Where: V CORE = DC value of the output or V ID voltage
V IN = DC value of the input or supply voltage
used to maintain V CORE within limits under transient
conditions.
L
F SW
= value of the inductor
= switching frequency
With a high dv/dt load transient, typical of high performance
microprocessors, the largest deviations in output voltage
occur at the leading and trailing edges of the load transient.
In order to fully utilize the output-voltage tolerance range, the
output voltage is positioned in the upper half of the range
when the output is unloaded and in the lower half of the
range when the controller is under full load. This droop
compensation allows larger transient voltage deviations and
thus reduces the size and cost of the output ?lter
components.
R IN should be selected to give the desired “droop” voltage at
the normal full load current 50 μ A applied through the R ISEN
resistor (or at a different full load current if adjusted as under
“Over-Current, Selecting R ISEN ” above).
R IN = Vdroop / 50 μ A
For a Vdroop of 80mV, R IN = 1.6k ?
A resistor from the feedback pin to ground raises the output
voltage above VID when the output is unloaded. The offset
resistor, (R os ), is selected based on R IN and the amount of
desired no-load offset, (VOS).
R os = R IN x VID / VOS
Current Balancing
The detected currents are also used to balance the channel
currents.
Each channel’s current is compared to the average of all
channel currents, and the difference is used to create an
offset in that channel’s PWM comparator. The offset is in a
direction to reduce the imbalance.
The balancing circuit can not make up for a difference in
r DS(ON) between synchronous recti?ers. If a FET has a
higher r DS(ON) , the current through that channel will be
reduced.
Figures 8 and 9 show the inductor current of a two channel
system without and with current balancing.
Inductor Current
The inductor current in each channel of a multi-phase Buck
converter has two components. There is a current equal to
the load current divided by the number of channels (I LT / n),
and a sawtooth current, (i PK-PK ) resulting from switching.
The sawtooth component is dependent on the size of the
12
Example: For V CORE = 1.6V,
V IN = 12V,
L = 1.3 μ H,
F SW = 250kHz,
Then i PK-PK = 4.3A
25
20
15
10
5
0
FIGURE 8. TWO CHANNEL MULTIPHASE SYSTEM WITH
CURRENT BALANCING DISABLED
25
20
15
10
5
0
FIGURE 9. TWO CHANNEL MULTIPHASE SYSTEM WITH
CURRENT BALANCING ENABLED
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参数描述
HIP6303CB WAF 制造商:Harris Corporation 功能描述:
HIP6303CB-T 功能描述:IC REG CTRLR BUCK PWM 20-SOIC RoHS:否 类别:集成电路 (IC) >> PMIC - 稳压器 - DC DC 切换控制器 系列:- 标准包装:4,000 系列:- PWM 型:电压模式 输出数:1 频率 - 最大:1.5MHz 占空比:66.7% 电源电压:4.75 V ~ 5.25 V 降压:是 升压:无 回扫:无 反相:无 倍增器:无 除法器:无 Cuk:无 隔离:无 工作温度:-40°C ~ 85°C 封装/外壳:40-VFQFN 裸露焊盘 包装:带卷 (TR)
HIP6303EVAL1 制造商:INTERSIL 制造商全称:Intersil Corporation 功能描述:Microprocessor CORE Voltage Regulator Multi-Phase Buck PWM Controller
HIP6304 制造商:INTERSIL 制造商全称:Intersil Corporation 功能描述:Microprocessor CORE Voltage Regulator Multi-Phase Buck PWM Controller
HIP6304 WAF 制造商:Intersil Corporation 功能描述: