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参数资料
| 型号： | HIP6500CB |
| 厂商： | INTERSIL CORP |
| 元件分类： | 电源管理 |
| 英文描述： | Multiple Linear Power Controller with ACPI Control Interface |
| 中文描述： | 9-CHANNEL POWER SUPPLY SUPPORT CKT, PDSO20 |
| 封装： | PLASTIC, MS-013-AC, SOIC-20 |
| 文件页数： | 7/15页 |
| 文件大小： | 155K |
| 代理商： | HIP6500CB |
7
3V3SB (Pin 3)
This pin is the output of the internal 3.3V
SB
regulator
(V
OUT1
). This internal regulator operates continuously for as
long as the 5VSB bias voltage is applied to the HIP6500.
This pin is monitored for under-voltage events.
VCLK (Pin 6)
This pin is the output of the internal 2.5V clock chip regulator
(V
OUT4
). This internal regulator operates only in active
states (S0, S1/S2) and is shut off during any sleep state,
regardless of the configuration of the chip. This pin is
monitored for under-voltage events.
Description
Operation
The HIP6500 controls 5 output voltages (Refer to Figures 1,
2, and 3). It is designed for microprocessor computer
applications with 3.3V, 5V, 5VSB, and 12V bias input from an
ATX power supply. The IC is composed of two linear
controllers supplying the PCI slots’ 3.3V
AUX
power (V
OUT3
)
and the 2.5V RDRAM or 3.3V SDRAM memory power
(V
OUT2
), two linear regulators providing an always-present
3.3V
SB
(V
OUT1
), and a dedicated 2.5V clock chip supply
(V
OUT4
), a dual switch controller supplying the 5V
DUAL
voltage (V
OUT5
), as well as all the control and monitoring
functions necessary for complete ACPI implementation.
Initialization
The HIP6500 automatically initializes upon receipt of input
power. The Power-On Reset (POR) function continually
monitors the 5VSB input supply voltage, initiating 3.3V
SB
soft-start operation after exceeding POR threshold. At 3ms
(typically) after 3.3V
SB
finishes its ramp-up, the ENxVDL
status and the memory voltage (V
MEM
) setting are latched in
and the chip proceeds to ramp up the remainder of the
voltages, as required.
Operational Truth Tables
The EN3VDL and EN5VDL pins offer a choice of 4
configurations in terms of the overall system architecture
and supported features. Tables 1-3 describe the truth
combinations pertaining to each of the three outputs.
As seen in Table 1, EN3VDL simply controls whether the
3.3VDUAL plane remains powered up during S4/S5 sleep
state.
Similarly, Table 2 details the fact that EN5VDL status
controls whether the 5V
DUAL
plane supports the S3-S5
sleep states.
As seen in Table 3, 2.5/3.3V
MEM
output is maintained in S3
(suspend to RAM) sleep state only. The dual-voltage support
accommodates both SDRAM as well as RDRAM type
memories.
Not shown in any of the tables are the 3.3V
SB
and the
2.5V
CLK
outputs. The 3.3V
SB
output powers up as soon as
the 5VSB ATX output is available. The 2.5V
CLK
output
operation is restricted by the chip’s POR and is only
available in active state (S0, S1). For additional information,
see the soft-start sequence diagrams.
Additionally, the internal circuitry does not allow the
transition from an S3 (suspend to RAM) state to an S4/S5
(suspend to disk/soft off) state or vice versa. The only ‘legal’
transitions are from an active state (S0, S1) to a sleep state
(S3, S5) and vice versa.
TABLE 1. 3.3V
DUAL
OUTPUT (V
OUT3
) TRUTH TABLE
EN3VDL
S5
S3
3V3DL
COMMENTS
0
1
1
3.3V
S0, S1 States (Active)
0
1
0
3.3V
S3
0
0
1
Note
Maintains Previous State
0
0
0
3.3V
S4/S5
1
1
1
3.3V
S0, S1 States (Active)
1
1
0
3.3V
S3
1
0
1
Note
Maintains Previous State
1
0
0
0V
S4/S5
NOTE: Combination Not Allowed.
TABLE 2. 5V
DUAL
OUTPUT (V
OUT5
) TRUTH TABLE
EN5VDL
S5
S3
5VDL
COMMENTS
0
1
1
5V
S0, S1 States (Active)
0
1
0
0V
S3
0
0
1
Note
Maintains Previous State
0
0
0
0V
S4/S5
1
1
1
5V
S0, S1 States (Active)
1
1
0
5V
S3
1
0
1
Note
Maintains Previous State
1
0
0
5V
S4/S5
NOTE: Combination Not Allowed.
TABLE 3. 2.5/3.3V
MEM
OUTPUT (V
OUT2
) TRUTH TABLE
R
SEL
S5
S3
2.5/3.3V
MEM
COMMENTS
1k
1
1
2.5V
S0, S1 States (Active)
1k
1
0
2.5V
S3
1k
0
1
Note
Maintains Previous State
1k
0
0
0V
S5
10k
1
1
3.3V
S0, S1 States (Active)
10k
1
0
3.3V
S3
10k
0
1
Note
Maintains Previous State
10k
0
0
0V
S5
NOTE: Combination Not Allowed.
HIP6500
相关PDF资料 |
PDF描述 |
|---|---|
| HIP6500EVAL1 | Multiple Linear Power Controller with ACPI Control Interface |
| HIP6501 | Triple Linear Power Controller with ACPI Control Interface |
| HIP6501A | Triple Linear Power Controller with ACPI Control Interface(带ACPI控制接口的线性电源控制器) |
| HIP6501EVAL1 | Triple Linear Power Controller with ACPI Control Interface |
| HIP6501ACB | Triple Linear Power Controller with ACPI Control Interface |
相关代理商/技术参数 |
参数描述 |
|---|---|
| HIP6500CB-TS2490 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| HIP6500EVAL1 | 制造商:INTERSIL 制造商全称:Intersil Corporation 功能描述:Multiple Linear Power Controller with ACPI Control Interface |
| HIP6501 | 制造商:INTERSIL 制造商全称:Intersil Corporation 功能描述:Triple Linear Power Controller with ACPI Control Interface |
| HIP6501A | 制造商:INTERSIL 制造商全称:Intersil Corporation 功能描述:Triple Linear Power Controller with ACPI Control Interface |
| HIP6501A_04 | 制造商:INTERSIL 制造商全称:Intersil Corporation 功能描述:Triple Linear Power Controller with ACPI Control Interface |
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