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参数资料
| 型号： | HIP6602BCR |
| 厂商： | INTERSIL CORP |
| 元件分类： | 功率晶体管 |
| 英文描述： | FPGA 1600000 SYSTEM GATE 1.8 VOLT - NOT RECOMMENDED for NEW DESIGN |
| 中文描述： | 0.73 A 2 CHANNEL, HALF BRDG BASED MOSFET DRIVER, PQCC16 |
| 封装： | 5 X 5 MM, PLASTIC, MO-220VHHB, QFN-16 |
| 文件页数： | 8/12页 |
| 文件大小： | 319K |
| 代理商： | HIP6602BCR |
8
FN9076.5
July 22, 2005
ensure safe operation at the desired frequency for the
selected MOSFETs. The total chip power dissipation is
approximated as:
where f
sw
is the switching frequency of the PWM signal. Q
U
and Q
L
is the upper and lower gate charge determined by
MOSFET selection and any external capacitance added to
the gate pins. The I
DDQ
VCC product is the quiescent power
of the driver and is typically 40mW.
The 1.05 term is a correction factor derived from the
following characterization. The base circuit for characterizing
the drivers for different loading profiles and frequencies is
provided. C
U
and C
L
are the upper and lower gate load
capacitors. Decoupling capacitors [0.15μF] are added to the
PVCC and VCC pins. The bootstrap capacitor value in the
test circuit is 0.01μF.
The power dissipation approximation is a result of power
transferred to and from the upper and lower gates. But, the
internal bootstrap device also dissipates power on-chip
during the refresh cycle. Expressing this power in terms of
the upper MOSFET total gate charge is explained below.
The bootstrap device conducts when the lower MOSFET or
its body diode conducts and pulls the PHASE node toward
GND. While the bootstrap device conducts, a current path is
formed that refreshes the bootstrap capacitor. Since the
upper gate is driving a MOSFET, the charge removed from
the bootstrap capacitor is equivalent to the total gate charge
of the MOSFET. Therefore, the refresh power required by
the bootstrap capacitor is equivalent to the power used to
charge the gate capacitance of the upper MOSFETs.
where Q
LOSS
is the total charge removed from the bootstrap
capacitors and provided to the upper gate loads.
In Figure 2, C
U
and C
L
values are the same and frequency
is varied from 10kHz to 1.5MHz. PVCC and VCC are tied
together to a +12V supply.
Figure 3 shows the dissipation in the driver with 1nF loading
on both gates and each individually. Figure 4 is the same as
Figure 3 except the capacitance is increased to 3nF.
The impact of loading on power dissipation is shown in
Figure 5. Frequency is held constant while the gate
capacitors are varied from 1nF to 5nF. VCC and PVCC are
tied together and to a +12V supply. Figures 6, 7 and 8 show
the same characterization for PVCC tied to +5V instead of
+12V. The gate supply voltage, PVCC, within the HIP6602B
sets both upper and lower gate driver supplies at the same
5V level for the last three curves.
Test Circuit
P = 1.05 x f
SW
x V
PVCC
[
(Q
U1
+ Q
U2
) + (Q
L1
+ Q
L2
)
]
+ I
DDQ
x VCC
2
3
_
P
REFRESH
f
SW
Q
LOSS
V
PVCC
f
SW
Q
U
V
PVCC
=
=
BOOT1
UGATE1
PHASE1
LGATE1
PWM1
PVCC
0.15μF
VCC
0.15μF
100k
2N7002
2N7002
C
L
0.01μF
C
U
+5V OR +12V
+12V
H
UGATE2
PHASE2
LGATE2
100k
2N7002
2N7002
C
L
C
U
0.01μF
PGND
PWM2
GND
BOOT2
+5V OR +12V
FIGURE 1. HIP6602B TEST CIRCUIT
HIP6602B
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| HIP6602BCRZA | 功能描述:功率驱动器IC W/ANNEAL DL CH SYNCH CT BUCK MOSF DRVR RoHS:否 制造商:Micrel 产品:MOSFET Gate Drivers 类型:Low Cost High or Low Side MOSFET Driver 上升时间: 下降时间: 电源电压-最大:30 V 电源电压-最小:2.75 V 电源电流: 最大功率耗散: 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:SOIC-8 封装:Tube |
| HIP6602BCRZA-T | 功能描述:功率驱动器IC W/ANL DL CH SYNCHCT BUCK MOSF DRVR RoHS:否 制造商:Micrel 产品:MOSFET Gate Drivers 类型:Low Cost High or Low Side MOSFET Driver 上升时间: 下降时间: 电源电压-最大:30 V 电源电压-最小:2.75 V 电源电流: 最大功率耗散: 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:SOIC-8 封装:Tube |
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