参数资料
型号: HIP6603BCB
厂商: Intersil
文件页数: 8/12页
文件大小: 0K
描述: IC DRIVER MOSFET SYNC BUCK 8SOIC
标准包装: 98
配置: 高端和低端,同步
输入类型: PWM
电流 - 峰: 400mA
配置数: 1
输出数: 2
高端电压 - 最大(自引导启动): 15V
电源电压: 10.8 V ~ 13.2 V
工作温度: 0°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 8-SOIC(0.154",3.90mm 宽)
供应商设备封装: 8-SOIC
包装: 管件
HIP6601B, HIP6603B, HIP6604B
desired frequency for the selected MOSFETs. The power
Test Circuit
P = 1.05f sw ? --- V U Q + V L Q ? + I DDQ VCC
dissipated by the driver is approximated as:
3
? 2 U L ?
(EQ. 2)
+12V
+5V OR +12V
+5V OR +12V
0.01 μ F
PVCC
BOOT
2N7002
where f sw is the switching frequency of the PWM signal. V U and
V L represent the upper and lower gate rail voltage. Q U and Q L is
the upper and lower gate charge determined by MOSFET selection
0.15 μ F
VCC
UGATE
PHASE
C U
and any external capacitance added to the gate pins. The I DDQ
V CC product is the quiescent power of the driver and is typically
0.15 μ F
PWM
LGATE
2N7002
100k Ω
30mW.
The power dissipation approximation is a result of power
transferred to and from the upper and lower gates. But, the internal
bootstrap device also dissipates power on-chip during the refresh
cycle. Expressing this power in terms of the upper MOSFET total
1000
GND
C L
gate charge is explained below.
The bootstrap device conducts when the lower MOSFET or its
body diode conducts and pulls the PHASE node toward GND.
While the bootstrap device conducts, a current path is formed that
refreshes the bootstrap capacitor. Since the upper gate is driving a
MOSFET, the charge removed from the bootstrap capacitor is
equivalent to the total gate charge of the MOSFET. Therefore, the
800
600
400
C U = C L = 3nF
C U = C L = 2nF
C U = C L = 1nF
refresh power required by the bootstrap capacitor is equivalent to
the power used to charge the gate capacitance of the MOSFET.
200
C U = C L = 4nF
C U = C L = 5nF
VCC = PVCC = 12V
P REFRESH = --- f SW Q
= --- f SW Q V
1
2
V
LOSS PVCC
1
2 U U
(EQ. 3)
0
500
1000
FREQUENCY (kHz)
1500
2000
FIGURE 1. POWER DISSIPATION vs FREQUENCY
where Q LOSS is the total charge removed from the bootstrap
capacitor and provided to the upper gate load.
1000
The 1.05 factor is a correction factor derived from the following
characterization. The base circuit for characterizing the drivers for
different loading profiles and frequencies is provided. C U and C L
are the upper and lower gate load capacitors. Decoupling capacitors
[0.15 μ F] are added to the PVCC and VCC pins. The bootstrap
capacitor value is 0.01 μ F.
In Figure 1, C U and C L values are the same and frequency is
varied from 50kHz to 2MHz. PVCC and VCC are tied together to
a +12V supply. Curves do exceed the 800mW cutoff, but
continuous operation above this point is not recommended.
800
600
400
200
VCC = PVCC = 12V
C U = C L = 3nF
C U = 3nF
C L = 0nF
C U = 0nF
C L = 3nF
Figure 2 shows the dissipation in the driver with 3nF loading on
both gates and each individually. Note the higher upper gate power
0
500 1000 1500
FREQUENCY (kHz)
FIGURE 2. 3nF LOADING PROFILE
2000
dissipation which is due to the bootstrap device refresh cycle.
Again PVCC and VCC are tied together and to a +12V supply.
8
The impact of loading on power dissipation is shown in
Figure 3. Frequency is held constant while the gate capacitors are
varied from 1nF to 5nF. VCC and PVCC are tied together and to a
+12V supply. Figures 4, 5 and 6 show the same characterization for
the HIP6603B with a +5V supply on PVCC and VCC tied to a +12V
supply.
Since both upper and lower gate capacitance can vary,
Figure 8 shows dissipation curves versus lower gate capacitance with
upper gate capacitance held constant at three different values. These
curves apply only to the HIP6601B due to power supply
configuration.
FN9072.8
May 1, 2012
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