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参数资料
| 型号： | HM62W8128LFP-10 |
| 元件分类： | SRAM |
| 英文描述： | 128K X 8 STANDARD SRAM, 100 ns, PDSO32 |
| 封装： | 0.525 INCH, PLASTIC, SOP-32 |
| 文件页数： | 5/16页 |
| 文件大小： | 84K |
| 代理商： | HM62W8128LFP-10 |
HM62W8128 Series
13
Low V
CC Data Retention Characteristics (Ta = 0 to +70°C)
Parameter
Symbol
Min
Typ
Max
Unit
Test Conditions
*3
V
CC for data retention
V
DR
2.0
—
V
CS1
≥ V
CC –0.2 V,
CS2
≥ V
CC –0.2 V or
0 V
≤ CS2 ≤ 0.2 V
Vin
≥ 0 V
Data retention current
I
CCDR (L-version)
—
1
50
*1
AV
CC = 3.0 V, Vin ≥ 0V
CS1
≥ V
CC – 0.2 V,
CS2
≥ V
CC – 0.2 V or
0 V
≤ CS2 ≤ 0.2 V
I
CCDR (L-SL version)
—
1
15
*2
A
Chip deselect to data retention
time
t
CDR
0
—
ns
See retention
waveform
Operation recovery time
t
R
5—
—
ms
Notes: 1. 20
A max at Ta = 0 to 40°C (L-version).
2. 3
A max at Ta = 0 to 40°C (L-SL version).
3. CS2 controls address buffer,
WE buffer, CS1 buffer, OE buffer, and Din buffer. If CS2 controls
data retention mode, Vin levels (address,
WE, OE, CS1, I/O) can be in the high impedance state. If
CS1 controls data retention mode, CS2 must be CS2
≥ V
CC – 0.2 V or 0 V ≤ CS2 ≤ 0.2 V.
The
other input levels (address,
WE, OE, I/O) can be in the high impedance state.
Low V
CC Data Retention Timing Waveform (1) (CS1 Controlled)
CC
V
3.0 V
2.2 V
0 V
CS1
tCDR
tR
CS1
V
– 0.2 V
CC
≥
DR1
V
Data retention mode
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