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| 型号： | HM6AEB36105BP40 |
| 元件分类： | SRAM |
| 英文描述： | 1M X 36 DDR SRAM, 0.45 ns, PBGA165 |
| 封装： | 15 X 17 MM, 1 MM PITCH, PLASTIC, FBGA-165 |
| 文件页数： | 1/24页 |
| 文件大小： | 261K |
| 代理商： | HM6AEB36105BP40 |
Rev.1.00 Sep 06, 2006 page 1 of 20
HM66AEB36105/HM66AEB18205
HM66AEB9405
36-Mbit DDR II SRAM Separate I/O
2-word Burst
REJ03C0047-0100
Rev.1.00
Sep.06.2006
Description
The HM66AEB36105 is a 1,048,576-word by 36-bit, the HM66AEB18205 is a 2,097,152-word by 18-bit, and the
HM66AEB9405 is a 4,194,304-word by 9-bit synchronous double data rate static RAM fabricated with advanced
CMOS technology using full CMOS six-transistor memory cell. It integrates unique synchronous peripheral circuitry
and a burst counter. All input registers controlled by an input clock pair (K and
K) and are latched on the positive edge
of K and
K. These products are suitable for applications which require synchronous operation, high speed, low voltage,
high density and wide bit configuration. These products are packaged in 165-pin plastic FBGA package.
Features
1.8 V ± 0.1 V power supply for core (V
DD)
1.4 V to V
DD power supply for I/O (VDDQ)
DLL circuitry for wide output data valid window and future frequency scaling
Separate independent read and write data ports
DDR read or write operation initiated each cycle
Separate data input/output bus
Two-tick burst for low DDR transaction size
Two input clocks (K and K) for precise DDR timing at clock rising edges only
Two output clocks (C and C) for precise flight time and clock skew matching-clock and data delivered together to
receiving device
Internally self-timed write control
Clock-stop capability with s restart
User programmable impedance output
Fast clock cycle time: 3.0 ns (333 MHz)/3.3 ns (300 MHz)/4.0 ns (250 MHz)/5.0 ns (200 MHz)/6.0 ns (167 MHz)
Simple control logic for easy depth expansion
JTAG boundary scan
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