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参数资料
| 型号： | HMC629LP4 |
| 厂商： | HITTITE MICROWAVE CORP |
| 元件分类： | 衰减器 |
| 英文描述： | 0 MHz - 6000 MHz RF/MICROWAVE VARIABLE ATTENUATOR, 5 dB INSERTION LOSS-MAX |
| 封装： | 4 X 4 MM, PLASTIC, LEADLESS, SMT, QFN-24 |
| 文件页数： | 4/8页 |
| 文件大小： | 885K |
| 代理商： | HMC629LP4 |
For price, delivery and to place orders: Hittite Microwave Corporation, 20 Alpha Road, Chelmsford, MA 01824
Phone: 978-250-3343
Fax: 978-250-3373
Order On-line at www.hittite.com
Application Support: Phone: 978-250-3343 or apps@hittite.com
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8 - 4
Parallel Mode (Direct Parallel Mode & Latched Parallel Mode)
Note: The parallel mode is enabled when P/S is set to low.
Direct Parallel Mode - The attenuation state is changed by the Control Voltage Inputs directly. The LE (Latch Enable)
must be at a logic high to control the attenuator in this manner.
Latched Parallel Mode - The attenuation state is selected using the Control Voltage Inputs and set while the LE is in
the Low state. The attenuator will not change state while LE is Low. Once all Control Voltage Inputs are at the desired
states the LE is pulsed. See timing diagram below for reference.
HMC629LP4 / 629LP4E
v07.0410
3 dB LSB GaAs MMIC 4-BIT
DIGITAL ATTENUATOR, DC - 6 GHz
Timing Diagram (Latched Parallel Mode)
Bias Voltage
Vdd (Vdc)
Idd (Typ.) (mA)
5
2.0
Control Voltage Input
Attenuation State
D3
D2
D1
D0
High
Reference
I.L.
High
Low
3 dB
High
Low
High
6 dB
High
Low
High
12 dB
Low
High
24 dB
Any combination of the above states will provide an attenuation
approximately equal to the sum of the bits selected.
Truth Table
PUP Truth Table
LE
PUP1
PUP2
Attenuation State
0
45 dB
0
1
0
45 dB
0
1
45 dB
0
1
Insertion Loss
1
X
0 to 45 dB
Note: Power-Up with LE= 1 provides direct parallel operation with
D0 - D3.
Parameter
Typ.
Min. serial period, t
SCK
100 ns
Control set-up time, t
CS
20 ns
Control hold-time, t
CH
20 ns
LE setup-time, t
LN
10 ns
Min. LE pulse width, t
LEW
10 ns
Min LE pulse spacing, t
LES
630 ns
Serial clock hold-time from LE, t
CKN
10 ns
Hold Time, t
PH.
0 ns
Latch Enable Minimum Width, t
LEN
10 ns
Setup Time, t
PS
2 ns
Control Voltage Table
State
Vdd = +3V
Vdd = +5V
Low
0 to 0.5V @ <1 A
0 to 0.8V @ <1 A
High
2 to 3V @ <1 A
2 to 5V @ <1 A
Power-Up States
If LE is set to logic LOW at power-up, the logic state of
PUP1 and PUP2 determines the power-up state of the
part per PUP truth table. If the LE is set to logic HIGH
at power-up, the logic state of D3-D0 determines
the power-up state of the part per truth table. The
attenuator latches in the desired power-up state
approximately 200 ms after power-up.
Power-On Sequence
The ideal power-up sequence is: GND, Vdd, digital
inputs, RF inputs. The relative order of the digital
inputs are not important as long as they are powered
after Vdd / GND
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