参数资料
型号: HMP8156
厂商: Intersil Corporation
英文描述: NTSC/PAL Encoder
中文描述: 的NTSC / PAL编码器
文件页数: 13/40页
文件大小: 563K
代理商: HMP8156
13
Reset
The RESET pin is used to return the decoder to an initializa-
tion state. This pin should be used after a power-up to set
the part into a known state. The internal registers are
returned to their RESET state and the Serial I
2
C port is
returned to inactive state. The RESET pin is an active low
signal and should be asserted for minimum of 1 CLK cycle.
After a RESET or a software reset has occurred all output
pins are three-stated. The following pins must be pulled high
to ensure proper operation:
HSYNC
VSYNC
DVLD
ACTIVE
FIELD
A 10K or smaller pullup resistor to V
CC
is recommended.
/
CLK
Y
N
Y
0
Y
1
Y
2
t
DLY
DVLD
Y[7-0]
ACTIVE
t
DVLD
Cr
N
Cb
0
Cr
0
Cb
1
CbCr[7-0]
NOTE 1
NOTE 2
NOTES:
1. Y0 is the first active luminance pixel of a line. Cb0 and Cr0 are first active chrominance pixels in a line. Cb and Cr will alternate every cycle
due to the 4:2:2 subsampling.
2. Active is asserted for lines 22-262.5 and 285.5-525. DVLD is asserted for every valid pixel during both active and blanking regions. DVLD
is asserted during vertical and horizontal sync.
FIGURE 15A. OUTPUT TIMING 16-BIT MODE
LINES 1-21
(LINES 1-23.5)
(LINES 23.5-310)
(LINES 311-335)
(LINES 336-623.5)
LINES 263.5-284
NTSC M, N PAL M
(PAL B, D, G, H, I, N COMB N)
(PAL B, D, G, H, I, N COMB N)
NTSC M, N PAL M
FIGURE 15B. ACTIVE VIDEO REGIONS IN 16-BIT MODE
<- PIXEL 0
LINES 285-525
<- PIXEL 0
LINES 22-263.5
PIXEL 1
PIXEL 2
PIXEL 3
PIXEL N
PIXEL N-1
PIXEL N-2
PIXEL N-3
CLK
DVLDY
t
DLY
Y[7-0]
ACTIVE
t
DVLD
Cb
0
Y
0
Cr
0
Y
1
Cb
2
Y
2
Cr
2
FIGURE 16. OUTPUT TIMING 8-BIT MODE
HMP8112
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