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参数资料
| 型号： | HMP8156ACN |
| 厂商： | INTERSIL CORP |
| 元件分类： | 颜色信号转换 |
| 英文描述： | NTSC/PAL Encoders |
| 中文描述： | COLOR SIGNAL ENCODER, PQFP64 |
| 封装： | 14 X 14 MM, PLASTIC, MS-022BE, MQFP-64 |
| 文件页数： | 18/40页 |
| 文件大小： | 563K |
| 代理商： | HMP8156ACN |
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TABLE 20. HORIZONTAL SYNC END TIME REGISTER
DESTINATION ADDRESS = 0E
H
BIT
NUMBER
FUNCTION
DESCRIPTION
RESET
STATE
7 - 0
Horizontal Drive
Programmable End
Time
This register provides a programmable delay for the external HDRIVE signal. The end
time of the HDRIVE pulse is set from the detection of horizontal sync in the video data.
HDRIVE is programmable in CLK increments and has a fixed 1 clock delay following the
falling edge of horizontal sync. This is the lower byte of the 10-bit word.
0010 0000
B
TABLE 21. HORIZONTAL SYNC END TIME REGISTER
DESTINATION ADDRESS = 0F
H
BIT
NUMBER
FUNCTION
DESCRIPTION
RESET
STATE
15 - 10
Not Used
Write Ignored, Read 0’s
XXXX XX
9 - 8
Horizontal Drive
Programmable End
Time
This register provides a programmable delay for the external HDRIVE signal. The end
time of the HDRIVE pulse is set from the detection of horizontal sync in the video data.
HDRIVE is programmable in CLK increments and has a fixed 1 clock delay following the
falling edge of horizontal sync. This is the upper byte of the 10-bit word.
00
B
TABLE 22. PHASE LOCKED LOOP ADJUST REGISTER
DESTINATION ADDRESS = 10
H
BIT
NUMBER
FUNCTION
DESCRIPTION
RESET
STATE
7 - 0
Phase Locked Loop
Filter Adjust Test
Register
The Phase Locked Loop time constants can be changed for testing purposes. It is rec-
ommended that the default value of (20
H
) always be used. The reset state is 00
H
.
0000 0000
B
TABLE 23. PHASE LOCKED LOOP SYNC DETECT WINDOW REGISTER
DESTINATION ADDRESS = 11
H
BIT
NUMBER
FUNCTION
DESCRIPTION
RESET
STATE
7 - 0
Phase Locked Loop
Horizontal Sync
Detect Window
These bits control the PLL horizontal sync detect window. This window sets the length
of time that the line lock PLL will allow the detection of the HSYNC. HSYNC outside of
this window are declared missing and will cause the missing sync logic to start counting
missing syncs. For NTSC this value should be DD
H
and for PAL, FF
H
.
1101 1101
B
TABLE 24. DC RESTORE START TIME REGISTER
DESTINATION ADDRESS = 12
H
BIT
NUMBER
FUNCTION
DESCRIPTION
RESET
STATE
7 - 0
DC Restore
Programmable Start
Time
This register provides a programmable delay for the internal DC RES signal. The start
time of the DC RES pulse is set from the detection of horizontal sync in the video data.
DC RES is programmable in CLK increments and has a fixed 1 clock delay following the
falling edge of horizontal sync. This signal is used to run the GATE B pin of the A/D con-
verter. This is the lower byte of the 10-bit word.
0011 0111
B
HMP8112
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相关代理商/技术参数 |
参数描述 |
|---|---|
| HMP8156ACNZ | 功能描述:编码器、解码器、复用器和解复用器 W/ANNEAL 64MQFP 0+70 ENCODER RoHS:否 制造商:Micrel 产品:Multiplexers 逻辑系列:CMOS 位数: 线路数量（输入/输出）:2 / 12 传播延迟时间:350 ps, 400 ps 电源电压-最大:2.625 V, 3.6 V 电源电压-最小:2.375 V, 3 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:QFN-44 封装:Tray |
| HMP8156CN | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| HMP8156EVAL1 | 制造商:INTERSIL 制造商全称:Intersil Corporation 功能描述:NTSC/PAL Encoders |
| HMP8156EVAL2 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| HMP8170 | 制造商:INTERSIL 制造商全称:Intersil Corporation 功能描述:NTSC/PAL Video Encoder |
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