参数资料
型号: HMS30C2000
英文描述: [Application Specific Solution Product]
中文描述: [专用解决方案产品]
文件页数: 17/161页
文件大小: 973K
代理商: HMS30C2000
HMS30C7110
2003 MagnaChip Semiconductor Ltd. All Rights Reserved
Version 1.5
17
1.3.
Pin Assignments
Table 1.1 PQFP Pin List
Pin #
Pin Name
I O
Pad
Type
Description
1
MODE
I
PICD
Operation Mode
MODE
TESTSE
Contents
0
0
Normal Operation
0
1
NANDTREE/BIST/PLL Test
1
0
Parallel Capture for ATPG
1
1
Scan Shift for ATPG
Test Scan Enable. Refer to the description for Pin 1
2
TESTSE
I
PICD
3
nRESET
I
PICS
System Reset, active low
4
VSSP
P
VSS for IO
5
MCLK
I
PICS
SDRAM Memory Feedback Clock
6
SCLK
O
POC8A
SDRAM clock
7
VSSI
P
VSS for core
8
ADDR21/Endian
BD
PBCD8A
Address Bus/Endian at Reset period. . Pulled down internally over 50 Kohm.
0: Little Endian (Default)
1: Big Endian
9
ADDR20/Boot32
BD
PBCD8A
Address Bus/Boot32 at Reset period. Pulled down internally over 50 Kohm.
0: 16-bit booting(Default)
1: 32-bit booting
10
ADDR19/Boot16-8
BU
PBCU8A
Address Bus/Boot16-8 at Reset. Pulled up internally over 50 Kohm.
0: 8-bit booting
1: 16-bit booting(Default)
11
ADDR18/Bypass
BU
PBCU8A
Address Bus/Bypass Internal Power-On-Reset Circuit. Pulled up internally over
50 Kohm. The active output width is over 1.5 Sec when 10MHz main clock is
used.
0: Use internal Power-On-Reset ciruit
1: Bypass internal Power-On-Reset circuit (Default)
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