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参数资料
型号： HMS30C7110
厂商： Electronic Theatre Controls, Inc.
元件分类： 网络处理器
英文描述： Multipurpose Network Processor
中文描述： 多功能网络处理器
文件页数： 7/161页
文件大小： 973K
代理商： HMS30C7110
HMS30C7110
2003 MagnaChip Semiconductor Ltd. All Rights Reserved
Version 1.5
7
Tables
Table 1.1 PQFP Pin List..............................................................................................17
Table 1.2 Pin Description............................................................................................26
Table 2.1 Power-up Configuration.............................................................................32
Table 2.2 System Memory Map : SDRAM_REMAP = 0.............................................33
Table 2.3 System Memory Map : SDRAM_REMAP = 1.............................................34
Table 2.4 Register Map at AMBA Peri-Bus...............................................................35
Table 2.5 Register Map at AMBA Host-Bus..............................................................37
Table 2.6 Cache and Write Buffer Control Register .................................................42
Table 2.7 Registers for PLL & Watchdog Timer.......................................................47
Table 2.8 PLL control..................................................................................................47
Table 2.9 Watch Dog Timer control...........................................................................48
Table 2.10 Watch Dog Timer Interval........................................................................48
Table 2.11 Main PLL Control......................................................................................49
Table 2.12 PLL Status.................................................................................................50
Table 2.13 Registers for ROM controller...................................................................54
Table 2.14 Configuration Registers Bit Definition.....................................................54
Table 2.15 Registers for SDRAM controller..............................................................59
Table 2.16 Configuration register ..............................................................................59
Table 2.17 Timing register .........................................................................................60
Table 2.18 Refresh Interval........................................................................................61
Table 2.19 INIT Control register................................................................................62
Table 2.20 Address Control register..........................................................................63
Table 2.21 Initialization Sequence..............................................................................65
Table 2.22 Registers for Ethernet MAC.....................................................................71
Table 2.23 MAC Mode Register Bit Definition ..........................................................73
Table 2.24 Interrupt Source Bit Definition.................................................................75
Table 2.25 Interrupt Enable Bit Definition.................................................................76
Table 2.26 Inter-Frame Gap Register........................................................................79
Table 2.27 Collision Configuration Definition............................................................80
Table 2.28 Transmit Buffer Address..........................................................................80
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