- 您现在的位置：买卖IC网 > PDF目录296196 > HSTL16918DGG (NXP SEMICONDUCTORS) 9-bit to 18-bit HSTL-to-LVTTL memory address latch PDF资料下载
参数资料
| 型号： | HSTL16918DGG |
| 厂商： | NXP SEMICONDUCTORS |
| 元件分类： | 锁存器 |
| 英文描述： | 9-bit to 18-bit HSTL-to-LVTTL memory address latch |
| 中文描述： | HSTL SERIES, LOW LEVEL TRIGGERED D LATCH, TRUE OUTPUT, PDSO48 |
| 封装： | PLASTIC, TSSOP-48 |
| 文件页数： | 2/8页 |
| 文件大小： | 65K |
| 代理商： | HSTL16918DGG |
Philips Semiconductors
Product data
HSTL16918
9-bit to 18-bit HSTL-to-LVTTL memory address latch
2
2001 Jun 16
853-2258 26484
FEATURES
Inputs meet JEDEC HSTL Std. JESD 8–6, and outputs meet
Level III specifications
ESD classification testing is done to JEDEC Standard JESD22.
Protection exceeds 2000 V to HBM per method A114.
Latch-up testing is done to JEDEC Standard JESD78, which
exceeds 100 mA.
Packaged in 48-pin plastic thin shrink small outline package
(TSSOP48)
DESCRIPTION
The HSTL16918 is a 9-bit to 18-bit D-type latch designed for
3.15 to 3.45 V VCC operation. The D inputs accept HSTL levels and
the Q outputs provide LVTTL levels.
The HSTL16918 is particularly suitable for driving an address bus to
two banks of memory. Each bank of nine outputs is controlled with
its own latch-enable (LE) input.
Each of the nine D inputs is tied to the inputs of two D-type latches
that provide true data (Q) at the outputs. While LE is LOW the Q
outputs of the corresponding nine latches follow the D inputs. When
LE is taken HIGH, the Q outputs are latched at the levels set up at
the D inputs.
The HSTL16918 is characterized for operation from 0 to +70
°C.
PIN CONFIGURATION
SW00768
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
2Q1
1Q1
GND
D1
D2
VCC
D3
GND
1LE
GND
VREF
GND
2LE
GND
D4
D5
D6
D7
VCC
D8
GND
2Q7
1Q7
VCC
2Q6
1Q6
GND
2Q5
1Q5
GND
2Q4
1Q4
VCC
2Q3
1Q3
GND
2Q2
1Q2
VCC
21
22
23
24
25
26
27
28
D9
GND
2Q9
1Q9
VCC
2Q8
1Q8
ORDERING INFORMATION
PACKAGES
TEMPERATURE RANGE
ORDER CODE
DWG NUMBER
48-pin plastic thin shrink small outline package
(TSSOP48)
0 to +70
°C
HSTL16918DGG
SOT362-1
相关PDF资料 |
PDF描述 |
|---|---|
| HV3-2405E-9 | 4.65 V-5.35 V ADJUSTABLE POSITIVE REGULATOR, PDIP8 |
| HV3-2405E-5 | 4.65 V-5.35 V ADJUSTABLE POSITIVE REGULATOR, PDIP8 |
| HVK89B | VHF-UHF BAND, 32 V, SILICON, VARIABLE CAPACITANCE DIODE |
| HVM27WK | 57 pF, SILICON, VARIABLE CAPACITANCE DIODE |
| HWD1487 | Low-Power, Slew-Rate-Limited RS-485/RS-422 Transceivers |
相关代理商/技术参数 |
参数描述 |
|---|---|
| HSTL16918DGG,112 | 功能描述:闭锁 DLatch 9Inputs LVTTL 3.3V 24mA RoHS:否 制造商:Micrel 电路数量:1 逻辑类型:CMOS 逻辑系列:TTL 极性:Non-Inverting 输出线路数量:9 高电平输出电流: 低电平输出电流: 传播延迟时间: 电源电压-最大:12 V 电源电压-最小:5 V 最大工作温度:+ 85 C 最小工作温度:- 40 C 封装 / 箱体:SOIC-16 封装:Reel |
| HSTL16918DGG,118 | 功能描述:闭锁 DLatch 9Inputs LVTTL 3.3V 24mA RoHS:否 制造商:Micrel 电路数量:1 逻辑类型:CMOS 逻辑系列:TTL 极性:Non-Inverting 输出线路数量:9 高电平输出电流: 低电平输出电流: 传播延迟时间: 电源电压-最大:12 V 电源电压-最小:5 V 最大工作温度:+ 85 C 最小工作温度:- 40 C 封装 / 箱体:SOIC-16 封装:Reel |
| HSTL16918DGG,512 | 功能描述:闭锁 9-18BT HSTL-LVTTL RoHS:否 制造商:Micrel 电路数量:1 逻辑类型:CMOS 逻辑系列:TTL 极性:Non-Inverting 输出线路数量:9 高电平输出电流: 低电平输出电流: 传播延迟时间: 电源电压-最大:12 V 电源电压-最小:5 V 最大工作温度:+ 85 C 最小工作温度:- 40 C 封装 / 箱体:SOIC-16 封装:Reel |
| HSTL16918DGG,518 | 功能描述:闭锁 9-18BT HSTL-LVTTL RoHS:否 制造商:Micrel 电路数量:1 逻辑类型:CMOS 逻辑系列:TTL 极性:Non-Inverting 输出线路数量:9 高电平输出电流: 低电平输出电流: 传播延迟时间: 电源电压-最大:12 V 电源电压-最小:5 V 最大工作温度:+ 85 C 最小工作温度:- 40 C 封装 / 箱体:SOIC-16 封装:Reel |
| HSTL16918DGG-T | 功能描述:闭锁 9-18BT HSTL-LVTTL MEM DR LATCH RoHS:否 制造商:Micrel 电路数量:1 逻辑类型:CMOS 逻辑系列:TTL 极性:Non-Inverting 输出线路数量:9 高电平输出电流: 低电平输出电流: 传播延迟时间: 电源电压-最大:12 V 电源电压-最小:5 V 最大工作温度:+ 85 C 最小工作温度:- 40 C 封装 / 箱体:SOIC-16 封装:Reel |
发布紧急采购，3分钟左右您将得到回复。