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| 型号： | HT86072(68PLCC) |
| 英文描述： | Microcontroller |
| 中文描述： | 微控制器 |
| 文件页数： | 13/28页 |
| 文件大小： | 195K |
| 代理商： | HT86072(68PLCC) |
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HT86XXX
Rev. 1.00
13
November 1, 2002
Stack register
Stack
The stack register is a special part of the memory used
to save the contents of the program counter (PC). This
stack is organized into eight levels. It is neither part of
the data nor part of the program space, and cannot be
read or written to. Its activated level is indexed by a
stack pointer (SP) and cannot be read or written to. At a
subroutine call or interrupt acknowledgement, the con-
tentsoftheprogramcounterarepushedontothestack.
The program counter is restored to its previous value
from the stack at the end of subroutine or interrupt rou-
tine, which is signaled by return instruction (RET or
RETI). After a chip resets, SP will point to the top of the
stack.
The interrupt request flag will be recorded but the ac-
knowledgment will be inhibited when the stack is full and
a non-masked interrupt takes place. After the stack
pointer is decremented (by RET or RETI), the interrupt
request will be serviced. This feature prevents stack
overflow and allows programmers to use the structure
more easily. In a similar case, if the stack is full and a
CALL is subsequently executed, stack overflow oc-
curs and the first entry is lost.
Data memory
RAM
The data memory is designed with 208 8 bits. The data
memory is further divided into two functional groups,
namely, special function registers (00H~2AH) and gen-
eral purpose user data memory (30H~FFH). Although
mostofthemcanbereadorbewrittento,someareread
only.
The special function registers include an indirect ad-
dressing register (R0:00H), memory pointer register
(MP0:01H), accumulator (ACC:05H), program counter
lower-order byte register (PCL:06H), table pointer
(TBLP:07H), table higher-order byte register
(TBLH:08H), status register (STATUS:0AH), interrupt
control register 0 (INTC:0BH), Timer/Event Counter 0
(TMR0H:0CH,TMR0L:0DH), Timer/Event Counter 0
control register (TMR0C:0EH), Timer/Event Counter 1
(TMR1H:0FH, TMR1L:10H), Timer/Event Counter 1
control register (TMR1C:11H), I/O registers
(PA:12H,PB:14H,PC:16H), I/O control registers
(PAC:13H,PBC:15H,PCC:17H), voice ROM address
latch0[23:0] (LATCH0H:18H, LATCH0M:19H,
LATCH0L:1AH), voice ROM address latch1[23:0]
(LATCH1H:1BH, LATCH1M:1CH, LATCH1L:1DH), in-
terrupt control register 1 (INTCH:1EH), table pointer
higher-order byte register (TBHP:1FH), Timer Counter
2 (TMR2H:20H, TMR2L:21H), Timer Counter 2 control
register (TMR2C:22H), Timer Counter 3 (TMR3L:24H),
Timer Counter 3 control register (TMR3C:25H), voice
control register (VOICEC:26H), DAC output
(DAH:27H,DAL:28H), volume control register
(VOL:29H), voice ROM latch data register
(LATCHD:2AH).
The general purpose data memory, addressed from
30H~FFH, is used for data and control information un-
der instruction commands.
The areas in the RAM can directly handle the arithmetic,
logic, increment, decrement, and rotate operations. Ex-
cept some dedicated bits, each bit in the RAM can be
set and reset by SET [m].i and CLR [m].i . They are
also indirectly accessible through the memory pointer
register 0 (MP0:01H) or the Memory Pointer register 1
(MP1:03H).
Address RAM Mapping
Read/Write
Description
00H
R0
R/W
Indirect addressing register 0
01H
MP0
R/W
Memory pointer 0
02H
R1
R/W
Indirect addressing register 1
03H
MP1
R/W
Memory pointer 1
04H
Unused
05H
ACC
R/W
Accumulator
06H
PCL
R/W
Program counter lower-order byte address
07H
TBLP
R/W
Table pointer lower-order byte address
08H
TBLH
R
Table higher-order byte content register
09H
WDTS
R/W
Watchdog Timer option setting register
0AH
STATUS
R/W
Status register
0BH
INTC
R/W
Interrupt control register 0
0CH
TMR0H
R/W
Timer/Event counter 0 higher-byte register
0DH
TMR0L
R/W
Timer/Event counter 0 lower-byte register
0EH
TMR0C
R/W
Timer/Event counter 0 control register
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