参数资料
型号: HW-V4-ML403-UNI-G-J
厂商: Xilinx Inc
文件页数: 32/32页
文件大小: 0K
描述: EVALUATION PLATFORM VIRTEX-4
产品变化通告: Development System Discontinuation 27/Aug/2012
标准包装: 1
系列: Virtex®-4
类型: FPGA
适用于相关产品: XC4VFX12-FF668-10C
所含物品: 评估平台,小型闪存卡 - 不包括电源 -
Configuration Options
R
Platform Flash Memory
The Platform Flash memory can also be used to program the FPGA. The Platform Flash
memory can hold up to four configuration images, which are selectable by the two least
significant bits of the configuration address DIP switches.
Note: ML402 Platform Flash memory can hold two configuration images, which are selectable by
the least significant bit of the configuration address DIP switches.
The board is wired so the Platform Flash memory can download bitstreams in Master
Serial, Slave Serial, Master SelectMAP (parallel), or Slave SelectMAP (parallel) modes.
Using the iMPACT tool to program the Platform Flash memory, the user has the option to
select which of the four modes to use for programming the FPGA. The configuration mode
DIP switches on the board must be set to match the programming method being used by
the Platform Flash memory.
The configuration source selector switch should be in the Plat Flash setting if the use of
Platform Flash memory is desired.
When set correctly, the Platform Flash memory programs the FPGA upon power-up or
whenever the Prog button is pressed.
Linear Flash + CPLD
Data stored in the linear flash can be read by the CPLD and used to program the FPGA.
Depending on the logic design in the CPLD, up to eight configuration images can
theoretically be supported.
Note: Note: ML402 linear flash can hold up to four configuration images.
The board is wired so the CPLD can download bitstreams via Master Serial, Slave Serial,
Master SelectMAP (parallel), or Slave SelectMAP (parallel) modes. The configuration
mode DIP switches on the board must be set to match the programming method being
used by the CPLD.
The configuration source selector switch should be in the CPLD Flash setting if the use of
CPLD + Platform Flash is desired.
When set correctly, the CPLD programs the FPGA upon power-up or whenever the Prog
button is pressed.
32
ML401/ML402/ML403 Evaluation Platform
UG080 (v2.5) May 24, 2006
相关PDF资料
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HW-V4-ML405-UNI-G-J EVALUATION PLATFORM VIRTEX-4
HW-V4-ML410-UNI-G-J EVALUATION PLATFORM VIRTEX-4
HW-V5-ML501-UNI-G EVALUATION PLATFORM VIRTEX-5
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HW-V5-ML550-UNI-G EVALUATION PLATFORM VIRTEX-5
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