参数资料
型号: HW-V5-ML525-FXT-UNI-G-J
厂商: Xilinx Inc
文件页数: 18/36页
文件大小: 0K
描述: EVAL BD ROCKETIO GTX VIRTEX5 JPN
产品培训模块: Virtex-5 Overview
Virtex™ 5 Power Estimation and Measurement Demonstration
产品变化通告: Development Systems Discontinuation 11/Oct/2010
标准包装: 1
系列: Virtex®-5 FXT
类型: FPGA
适用于相关产品: XC5VFX200T-FF1738CES
所含物品: 板 - 不包括电源 -
配用: HW-XGI-SCLK-G-ND - MODULE SUPER CLOCK
HW-AFX-SMA-SFP-ND - CONVERSION MODULE SMA - SFP
HW-AFX-SMA-SATA-ND - CONVERSION MODULE SMA - SATA
HW-AFX-SMA-RJ45-ND - CONVERSION MODULE SMA - RJ45
HW-AFX-SMA-NQSL-G-ND - NQSL NELCO QUAD SERIAL LOOP
HW-AFX-SMA-HSSDC2-ND - CONVERSION MODULE SMA - HSSDC2
HW-AFX-BERG-SDRAM-ND - EXPANSION MOD SDRAM BERG-SDRAM
相关产品: XC5VLX330T-2FFG1738C-ND - IC FPGA VIRTEX-5 330K 1738FBGA
XC5VLX330T-2FF1738C-ND - IC FPGA VIRTEX-5 330K 1738FBGA
XC5VLX330T-1FFG1738I-ND - IC FPGA VIRTEX-5 330K 1738FBGA
XC5VLX330T-1FFG1738C-ND - IC FPGA VIRTEX-5 330K 1738FBGA
XC5VLX330T-1FF1738I-ND - IC FPGA VIRTEX-5 330K 1738FBGA
XC5VLX330T-1FF1738C-ND - IC FPGA VIRTEX-5 330K 1738FBGA
Detailed Description
R
12. Oscillator Sockets
The ML52x platform has two oscillator sockets, each wired for standard LVCMOS-type
oscillators. These connect to the DUT clock pins as shown in Table 7 . The oscillator sockets
accept both half- and full-sized oscillators and are powered by 3.3V or the VCCAUX 2.5V
power supply.
Table 7:
Oscillator Sockets Connections
Ref Des
Enable/Disable Power Select
Jumper Jumper
Pin Name
ML521
ML523
ML525
X2
X3
J114
J117
J115
J116
CLK_IN_B
CLK_IN_A
AB19
D18 (1)
AG21
J19 (1)
AP27
K29
Notes:
1. For ML521 and ML523, the X3 clock input is not placed on the master clock IOB site. The environment
variable XIL_PLACE_ALLOW_LOCAL_BUFG_ROUTING must be set to demote this condition to a
warning and allow the design to continue.
13. Single-Ended SMA Clock Inputs
The ML52x platform has two single-ended clock input SMA connections that allow
connection to an external function generator. These connect to the DUT clock pins as
shown in Table 8 .
Table 8:
SMA Clock Pin Connections
Ref Des
J123
J124
Pin Name
CLK_B
CLK_A
ML521
AB17 (1)
E17
ML523
AF19 (1)
K18
ML525
AM27
M27
Notes:
1. For ML521 and ML523, the J123 clock input is not placed on the master clock IOB site. The environment
variable XIL_PLACE_ALLOW_LOCAL_BUFG_ROUTING must be set to demote this condition to a
warning and allow the design to continue.
14. Differential SMA Global Clock Inputs
The ML52x platform has two pairs of differential SMA transceivers clock inputs that allow
connection to an external function generator. These connect to the DUT clock pins as
shown in Table 9 .
Table 9:
Differential SMA clock connections
18
Ref Des
J120
J125
J121
J122
Pin Name
CLK_DIFF_A_P
CLK_DIFF_A_N
CLK_DIFF_B_P
CLK_DIFF_B_N
ML521
E13
E12
AC12
AC13
ML523
J16
J17
AH15
AG15
ML525
L17
M17
AM16
AM17
ML52 x User Guide
UG225 (v2.1) August 4, 2010
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