- 您现在的位置：买卖IC网 > PDF目录384464 > HY29F800ABT-70I (HYNIX SEMICONDUCTOR INC) 8 Megabit (1Mx8/512Kx16), 5 Volt-only, Flash Memory PDF资料下载
参数资料
| 型号： | HY29F800ABT-70I |
| 厂商： | HYNIX SEMICONDUCTOR INC |
| 元件分类： | DRAM |
| 英文描述： | 8 Megabit (1Mx8/512Kx16), 5 Volt-only, Flash Memory |
| 中文描述： | 512K X 16 FLASH 5V PROM, 70 ns, PDSO48 |
| 封装： | TSOP-48 |
| 文件页数： | 13/40页 |
| 文件大小： | 279K |
| 代理商： | HY29F800ABT-70I |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页当前第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页
13
Rev. 1.1/Feb 02
HY29F800A
Commands written to the device during execution
of the Automatic Erase algorithm are ignored. Note
that a hardware reset immediately terminates the
erase operation. To ensure data integrity, the
aborted Chip Erase command sequence should
be reissued once the reset operation is complete.
When the Automatic Erase algorithm is finished,
the device returns to the Read mode. Several
methods are provided to allow the host to deter-
mine the status of the erase operation, as de-
scribed in the Write Operation Status section.
Figure 5 illustrates the Chip Erase procedure.
Sector Erase Command
The Sector Erase command sequence consists
of two unlock cycles, followed by the erase com-
mand, two additional unlock cycles and then the
sector erase data cycle, which specifies which
sector is to be erased. As described later in this
section, multiple sectors can be specified for era-
sure with a single command sequence. During
sector erase, all specified sectors are erased se-
quentially. The data in sectors not specified for
erasure, as well as the data in any protected sec-
tors, even if specified for erasure, is not affected
by the sector erase operation.
The Sector Erase command sequence starts the
Automatic Erase algorithm, which preprograms
and verifies the specified unprotected sectors for
an all zero data pattern prior to electrical erase.
The device then provides the required number of
internally generated erase pulses and verifies cell
erasure within the proper cell margins. The host
Figure 5. Chip Erase Procedure
START
Issue CHIP ERASE
Command Sequence
Check Erase Status
(See Write Operation Status
Section)
CHIP ERASE COMPLETE
GO TO
ERROR RECOVERY
DQ[5] Error Exit
Normal Exit
system is not required to provide any controls or
timings during these operations.
After the sector erase data cycle (the sixth bus
cycle) of the command sequence is issued, a sec-
tor erase time-out of 50 μs, measured from the
rising edge of the final WE# pulse in that bus cycle,
begins. During this time, an additional sector erase
data cycle, specifying the sector address of an-
other sector to be erased, may be written into an
internal sector erase buffer. This buffer may be
loaded in any sequence, and the number of sec-
tors specified may be from one sector to all sec-
tors. The only restriction is that the time between
these additional data cycles must be less than 50
μs, otherwise erasure may begin before the last
data cycle is accepted. To ensure that all data
cycles are accepted, it is recommended that host
processor interrupts be disabled during the time
that the additional cycles are being issued and then
be re-enabled afterwards.
Note:
The device is capable of accepting three ways of
invoking Erase Commands for additional sectors during
the time-out window. The preferred method, described
above, is the sector erase data cycle after the initial six
bus cycle command sequence. However, the device also
accepts the following methods of specifying additional
sectors during the sector erase time-out:
Repeat the entire six-cycle command sequence, speci-
fying the additional sector in the sixth cycle.
Repeat the last three cycles of the six-cycle command
sequence, specifying the additional sector in the third
cycle.
If all sectors scheduled for erasing are protected,
the device returns to reading array data after ap-
proximately 100 μs. If at least one scheduled sec-
tor is not protected, the erase operation erases
the unprotected sectors, and ignores the command
for the scheduled sectors that are protected.
The system can monitor DQ[3] to determine if the
50 μs sector erase time-out has expired, as de-
scribed in the Write Operation Status section. If
the time between additional sector erase data
cycles can be insured to be less than the time-
out, the system need not monitor DQ[3].
Any command other than Sector Erase or Erase
Suspend during the time-out period resets the
device to reading array data. The system must
then rewrite the command sequence, including any
additional sector erase data cycles. Once the sec-
tor erase operation itself has begun, only the Erase
相关PDF资料 |
PDF描述 |
|---|---|
| HY29F800ABT-90 | 8 Megabit (1Mx8/512Kx16), 5 Volt-only, Flash Memory |
| HY29F800ABT-90I | 8 Megabit (1Mx8/512Kx16), 5 Volt-only, Flash Memory |
| HY29F800ATG-12 | 8 Megabit (1Mx8/512Kx16), 5 Volt-only, Flash Memory |
| HY29F800ATG-12I | 8 Megabit (1Mx8/512Kx16), 5 Volt-only, Flash Memory |
| HY29F800ATG-55 | 8 Megabit (1Mx8/512Kx16), 5 Volt-only, Flash Memory |
相关代理商/技术参数 |
参数描述 |
|---|---|
| HY29F800ABT-90 | 制造商:HYNIX 制造商全称:Hynix Semiconductor 功能描述:8 Megabit (1Mx8/512Kx16), 5 Volt-only, Flash Memory |
| HY29F800ABT-90I | 制造商:HYNIX 制造商全称:Hynix Semiconductor 功能描述:8 Megabit (1Mx8/512Kx16), 5 Volt-only, Flash Memory |
| HY29F800ATG-12 | 制造商:HYNIX 制造商全称:Hynix Semiconductor 功能描述:8 Megabit (1Mx8/512Kx16), 5 Volt-only, Flash Memory |
| HY29F800ATG-12I | 制造商:HYNIX 制造商全称:Hynix Semiconductor 功能描述:8 Megabit (1Mx8/512Kx16), 5 Volt-only, Flash Memory |
| HY29F800ATG-55 | 制造商:HYNIX 制造商全称:Hynix Semiconductor 功能描述:8 Megabit (1Mx8/512Kx16), 5 Volt-only, Flash Memory |
发布紧急采购，3分钟左右您将得到回复。