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参数资料
| 型号： | HY29LV320TF-70I |
| 厂商： | HYNIX SEMICONDUCTOR INC |
| 元件分类： | DRAM |
| 英文描述： | 32 Mbit (2M x 16) Low Voltage Flash Memory |
| 中文描述： | 2M X 16 FLASH 3V PROM, 70 ns, PBGA63 |
| 封装： | 7 X 11 MM, FBGA-63 |
| 文件页数： | 12/44页 |
| 文件大小： | 323K |
| 代理商： | HY29LV320TF-70I |
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12
r1.3/May 02
HY29LV320
mode. In this mode, current consumption is greatly
reduced, and the data bus outputs are placed in
the high impedance state, independent of the OE#
input. The Standby mode can invoked using two
methods.
The device enters the
CE# Controlled
Deep
Standby
mode when the CE# and RESET# pins
are both held at V
CC
± 0.3V. Note that this is a
more restricted voltage range than V
IH
. If both
CE# and RESET# are held at V
IH
, but not within
V
CC
± 0.3V, the device will be in the
Normal Standby
mode, but the standby current will be greater.
Note:
If the device is deselected during erasure or
programming, it continues to draw active current until
the operation is completed.
The device enters the
RESET# Controlled Deep
Standby
mode when the RESET# pin is held at
V
SS
± 0.3V. If RESET# is held at V
IL
but not within
V
SS
± 0.3V, the standby current will be greater. See
RESET# section for additional information on the
reset operation.
The device requires standard access time (t
CE
)
for read access when the device is in any of the
standby modes before it is ready to read data.
Sleep Mode
The sleep mode automatically minimizes device
power consumption. This mode is automatically
entered when addresses remain stable for t
ACC
+
30 ns (typical) and is independent of the state of
the CE#, WE#, and OE# control signals. Standard
address access timings provide new data when
addresses are changed. While in sleep mode,
output data is latched and always available to the
system. The device does not enter sleep mode if
an automatic program or automatic erase algo-
rithm is in progress.
Output Disable Operation
When the OE# input is at V
IH
, output data from
the device is disabled and the data bus pins are
placed in the high impedance state.
Reset Operation
The RESET# pin provides a hardware method of
resetting the device to reading array data. When
the RESET# pin is driven low for the minimum
specified period, the device immediately termi-
nates any operation in progress, tri-states the data
bus pins, and ignores all read/write commands for
the duration of the RESET# pulse. The device also
resets the internal state machine to reading array
data. If an operation was interrupted by the as-
sertion of RESET#, it should be reinitiated once
the device is ready to accept another command
sequence to ensure data integrity.
Current is reduced for the duration of the RESET#
pulse as described in the Standby Operation sec-
tion.
If RESET# is asserted during a program or erase
operation (RY/BY# pin is Low), the RY/BY# pin
remains Low (busy) until the internal reset opera-
tion is complete, which requires a time of t
READY
(during Automatic Algorithms). The system can
thus monitor RY/BY# to determine when the reset
operation completes, and can perform a read or
write operation t
RB
after RY/BY# goes High. If
RESET# is asserted when a program or erase
operation is not executing (RY/BY# pin is High),
the reset operation is completed within a time of
t
RP
. In this case, the host can perform a read or
write operation t
RH
after the RESET# pin returns
High.
The RESET# pin may be tied to the system reset
signal. Thus, a system reset would also reset the
device, enabling the system to read the boot-up
firmware from the Flash memory.
Sector Group Protect Operation
The hardware sector group protection feature dis-
ables both program and erase operations in any
combination of sector groups. A sector group con-
sists of a single sector or a group of adjacent sec-
tors, as specified in Tables 6 and 7. This function
can be implemented either in-system or by using
programming equipment. It requires a high volt-
age (V
ID
) on the RESET# pin and uses standard
microprocessor bus cycle timing to implement
sector protection. The flow chart in Figure 3 illus-
trates the algorithm.
The HY29LV320 is shipped with all sectors un-
protected. It is possible to determine whether a
sector is protected or unprotected. See the Elec-
tronic ID Mode section for details.
Sector Unprotect Operation
The hardware sector unprotection feature re-en-
ables both program and erase operations in pre-
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| HY29LV320TF-80I | 32 Mbit (2M x 16) Low Voltage Flash Memory |
| HY29LV320TF-90I | 32 Mbit (2M x 16) Low Voltage Flash Memory |
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| HY29LV320TF-80 | 制造商:HYNIX 制造商全称:Hynix Semiconductor 功能描述:32 Mbit (2M x 16) Low Voltage Flash Memory |
| HY29LV320TF-80I | 制造商:HYNIX 制造商全称:Hynix Semiconductor 功能描述:32 Mbit (2M x 16) Low Voltage Flash Memory |
| HY29LV320TF-90 | 制造商:HYNIX 制造商全称:Hynix Semiconductor 功能描述:32 Mbit (2M x 16) Low Voltage Flash Memory |
| HY29LV320TF-90I | 制造商:HYNIX 制造商全称:Hynix Semiconductor 功能描述:32 Mbit (2M x 16) Low Voltage Flash Memory |
| HY29LV320TT-12 | 制造商:HYNIX 制造商全称:Hynix Semiconductor 功能描述:32 Mbit (2M x 16) Low Voltage Flash Memory |
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