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参数资料
| 型号： | HY51S65803HG(HGL) |
| 英文描述： | 8Mx8|3.3V|4K|45|FP/EDO DRAM - 64M |
| 中文描述： | 8Mx8 | 3.3 | 4K的| 45 |计划生育/ EDO公司的DRAM - 6400 |
| 文件页数： | 11/12页 |
| 文件大小： | 104K |
| 代理商： | HY51S65803HG(HGL) |
HY51V(S)16160HG/HGL
Rev.0.1/Apr.01
11
17. Access time is determined by the longest among t
AA
or t
CAC
or t
ACP
18. In delayed write or read-modify-write cycels, OE must disable output buffer prior to applying data to the
device, After /RAS is reset, if t
OEH
>=t
CWL
, the I/O pin will remain open circuit (high impedance)
If t
OEH
< t
CWL
, invalid data will be out at each I/O
19. When both /UCAS and /LCAS go low at the same time, all 16 bit data are written into the device
/UCAS and /LCAS cannot be staggered within the same write / read cycles.
20. All the Vcc and Vss pins shall be supplied with the same voltages
21. t
ASC
, t
CAH
, t
RCS
, t
WCS
, t
WCH
, t
CSR
and t
RPC
are determined by the earlier falling edge of /UCAS
or /LCAS.
22. t
CRP
, t
CHR
, t
RCH
, t
ACP
and t
CPW
are determined by the later rising edge of /UCAS or /LCAS.
23. t
CWL
, t
DH
, t
DS
and t
CSH
should be satisfied by both /UCAS and /LCAS
24. t
CP
is determined by that time the both /UCAS and /LCAS are high.
25. When output buffers are enabled once, sustain the low impedance state until valid data is obtained
When output buffer is turned on and off within a very short time, generally it causes large Vcc/Vss line
noise, which causes to degrade V
IH
min / V
IL
max level
26. Please do not use t
RASS
timing, 10us <= t
RASS
<= 100us. During this period, the device is in transition
state from normal operation mode to self refresh mode. If tRASS >= 100us, then /RAS precharge time
should use t
RPS
instead of t
RP
27. H or L ( H : V
IH
(min) <=V
IN
<= V
IH
(max), L : V
IL
(min) <= V
IN
<= V
IL
(max))
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