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参数资料
| 型号： | HY57V283220LT-5 |
| 厂商： | HYNIX SEMICONDUCTOR INC |
| 元件分类： | DRAM |
| 英文描述： | 4 Banks x 1M x 32Bit Synchronous DRAM |
| 中文描述： | 4M X 32 SYNCHRONOUS DRAM, 4.5 ns, PDSO86 |
| 封装： | 0.400 X 0.875 INCH, 0.50 MM PITCH, TSOP2-86 |
| 文件页数： | 3/15页 |
| 文件大小： | 916K |
| 代理商： | HY57V283220LT-5 |
Rev. 0.9 / July 2004
3
HY57V283220(L)T(P) / HY5V22(L)F(P)
PIN CONFIGURATION ( HY57V283220(L)T(P) Series)
/C S
B A 1
A 10/A P
A 2
V
D D
N C
V
D D
43
V
S S
44
0.5 m m p in p itch
/R A S
B A 0
A 1
D Q M 2
D Q 23
42
D Q 24
45
V
D D
D Q 0
V
D D Q
D Q 1
D Q 2
V
S S Q
D Q 3
D Q 4
V
D D Q
D Q 5
D Q 6
V
S S Q
D Q 7
N C
V
D D
D Q M 0
/W E
/C A S
A 11
A 0
D Q 16
V
S S Q
D Q 17
D Q 18
V
D D Q
D Q 19
D Q 20
V
S S Q
D Q 21
D Q 22
V
D D Q
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
V
S S
D Q 15
V
S S Q
D Q 14
D Q 13
V
D D Q
D Q 12
D Q 11
V
S S Q
D Q 10
D Q 9
V
D D Q
D Q 8
N C
V
S S
D Q M 1
N C
N C
C LK
C K E
A 9
A 8
A 7
A 6
A 5
A 4
A 3
D Q M 3
V
S S
N C
D Q 31
V
D D Q
D Q 30
D Q 29
V
S S Q
D Q 28
D Q 27
V
D D Q
D Q 26
D Q 25
V
S S Q
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
86 p in T S O P II
400m il x 875m il
PIN DESCRIPTION
PIN
PIN NAME
DESCRIPTION
CLK
Clock
The system clock input. All other inputs are registered to the SDRAM
on the rising edge of CLK.
CKE
Clock Enable
Controls internal clock signal and when deactivated, the SDRAM will be one
of the states among power down, suspend or self refresh
CS
Chip Select
Enables or disables all inputs except CLK, CKE and DQM
BA0, BA1
Bank Address
Selects bank to be activated during RAS activity
Selects bank to be read/written during CAS activity
A0 ~ A11
Address
Row Address : RA0 ~ RA11, Column Address : CA0 ~ CA7
Auto-precharge flag : A10
RAS, CAS, WE
Row Address Strobe,
Column Address Strobe,
Write Enable
RAS, CAS and WE define the operation
Refer function truth table for details
DQM0~3
Data Input/Output Mask
Controls output buffers in read mode and masks input data in write mode
DQ0 ~ DQ31
Data Input/Output
Multiplexed data input / output pin
V
DD
/V
SS
Power Supply/Ground
Power supply for internal circuits and input buffers
V
DDQ
/V
SSQ
Data Output Power/Ground
Power supply for output buffers
NC
No Connection
No connection
相关PDF资料 |
PDF描述 |
|---|---|
| HY57V283220LT-55 | 4 Banks x 1M x 32Bit Synchronous DRAM |
| HY57V283220LT-6 | 4 Banks x 1M x 32Bit Synchronous DRAM |
| HY57V283220LT-7 | 4 Banks x 1M x 32Bit Synchronous DRAM |
| HY57V283220LT-8 | 4 Banks x 1M x 32Bit Synchronous DRAM |
| HY57V283220LT-H | 4 Banks x 1M x 32Bit Synchronous DRAM |
相关代理商/技术参数 |
参数描述 |
|---|---|
| HY57V283220LT-55 | 制造商:HYNIX 制造商全称:Hynix Semiconductor 功能描述:4 Banks x 1M x 32Bit Synchronous DRAM |
| HY57V283220LT-6 | 制造商:HYNIX 制造商全称:Hynix Semiconductor 功能描述:4 Banks x 1M x 32Bit Synchronous DRAM |
| HY57V283220LT-7 | 制造商:HYNIX 制造商全称:Hynix Semiconductor 功能描述:4 Banks x 1M x 32Bit Synchronous DRAM |
| HY57V283220LT-8 | 制造商:HYNIX 制造商全称:Hynix Semiconductor 功能描述:4 Banks x 1M x 32Bit Synchronous DRAM |
| HY57V283220LT-H | 制造商:HYNIX 制造商全称:Hynix Semiconductor 功能描述:4 Banks x 1M x 32Bit Synchronous DRAM |
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