- 您现在的位置：买卖IC网 > PDF目录385422 > HY57V643220DTP-55 (HYNIX SEMICONDUCTOR INC) 4Banks x 512K x 32bits Synchronous DRAM PDF资料下载
参数资料
| 型号： | HY57V643220DTP-55 |
| 厂商： | HYNIX SEMICONDUCTOR INC |
| 元件分类： | DRAM |
| 英文描述： | 4Banks x 512K x 32bits Synchronous DRAM |
| 中文描述： | 2M X 32 SYNCHRONOUS DRAM, 5 ns, PDSO86 |
| 封装： | 0.400 X 0.875 INCH, 0.50 MM PITCH, LEAD FREE, TSOP2-86 |
| 文件页数： | 2/13页 |
| 文件大小： | 227K |
| 代理商： | HY57V643220DTP-55 |
This document is a general product description and is subject to change without notice. Hynix does not assume any responsibility for
use of circuits described. No patent licenses are implied.
Rev. 0.3 / Sep. 2004
2
HY57V643220D(L/S)T(P) Series
4Banks x 512K x 32bits Synchronous DRAM
DESCRIPTION
The Hynix HY57V643220D(L/S)T(P) series is a 67,108,864bit CMOS Synchronous DRAM, ideally suited for the memory
applications which require wide data I/O and high bandwidth. HY57V643220D(L/S)T(P) is organized as 4banks of
524,228x32.
HY57V643220D(L/S)T(P) is offering fully synchronous operation referenced to a positive edge of the clock. All inputs
and outputs are synchronized with the rising edge of the clock input. The data paths are internally pipelined to achieve
very high bandwidth. All input and output voltage levels are compatible with LVTTL.
Programmable options include the length of pipeline (Read latency of 2 or 3), the number of consecutive read or write
cycles initiated by a single control command (Burst length of 1,2,4,8 or full page), and the burst count sequence(se-
quential or interleave). A burst of read or write cycles in progress can be terminated by a burst terminate command or
can be interrupted and replaced by a new burst read or write command on any cycle. (This pipelined design is not re-
stricted by a '2N' rule)
FEATURES
Voltage : VDD, VDDQ 3.3V supply voltage
ORDERING INFORMATION
Note
1. HY57V643220DT(P) Series : Normal Power
2. HY57V643220DLT(P) Series : Low Power
3. HY57V643220DST(P) Series : Super Low Power
4. HY57V643220D(L/S)T Series : Leaded
5. HY57V643220D(L/S)TP Series : Lead Free
Part No.
Clock
Frequency
Organization
Interface
Package
HY57V643220D(L/S)T(P)-45
222MHz
4Banks x 512Kbits
x32
LVTTL
86pin TSOP-II
(Lead Free)
HY57V643220D(L/S)T(P)-5
200MHz
HY57V643220D(L/S)T(P)-55
183MHz
HY57V643220D(L/S)T(P)-6
166MHz
HY57V643220D(L/S)T(P)-7
143MHz
All device pins are compatible with LVTTL interface
JEDEC standard 400mil 86pin TSOP-II with 0.5mm of
pin pitch
All inputs and outputs referenced to positive edge of
system clock
Data mask function by DQM 0, 1, 2 and DQM 3
Internal four banks operation
Auto refresh and self refresh
4096 Refresh cycles / 64ms
Programmable Burst Length and Burst Type
- 1, 2, 4, 8 or full page for Sequential Burst
- 1, 2, 4 or 8 for Interleave Burst
Programmable CAS Latency ; 2, 3 Clocks
Burst Read Single Write operation
相关PDF资料 |
PDF描述 |
|---|---|
| HY57V643220DTP-6 | 4Banks x 512K x 32bits Synchronous DRAM |
| HY57V643220DTP-7 | 4Banks x 512K x 32bits Synchronous DRAM |
| HY57V643220DLT-45 | 4Banks x 512K x 32bits Synchronous DRAM |
| HY57V643220DLT-5 | 4Banks x 512K x 32bits Synchronous DRAM |
| HY57V643220DLT-55 | 4Banks x 512K x 32bits Synchronous DRAM |
相关代理商/技术参数 |
参数描述 |
|---|---|
| HY57V643220DTP-6 | 制造商:HYNIX 制造商全称:Hynix Semiconductor 功能描述:4Banks x 512K x 32bits Synchronous DRAM |
| HY57V643220DTP-7 | 制造商:HYNIX 制造商全称:Hynix Semiconductor 功能描述:4Banks x 512K x 32bits Synchronous DRAM |
| HY57V644010TC-10 | 制造商:未知厂家 制造商全称:未知厂家 功能描述:x4 SDRAM |
| HY57V644010TC-12 | 制造商:未知厂家 制造商全称:未知厂家 功能描述:x4 SDRAM |
| HY57V644010TC-15 | 制造商:未知厂家 制造商全称:未知厂家 功能描述:x4 SDRAM |
发布紧急采购，3分钟左右您将得到回复。