- 您现在的位置：买卖IC网 > PDF目录370740 > HY5DV651622T-G7 DDR Synchronous DRAM PDF资料下载
参数资料
| 型号： | HY5DV651622T-G7 |
| 英文描述： | DDR Synchronous DRAM |
| 中文描述： | DDR同步DRAM |
| 文件页数： | 3/27页 |
| 文件大小： | 273K |
| 代理商： | HY5DV651622T-G7 |
第1页第2页当前第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页
DESCRIPTION
The Hynix HY5DV281622 is a 134,217,728-bit CMOS Double Data Rate(DDR) Synchronous DRAM, ideally suited for the
point-to-point applications which requires high bandwidth.
The Hynix 8Mx16 DDR SDRAMs offer fully synchronous operations referenced to both rising and falling edges of the
clock. While all addresses and control inputs are latched on the rising edges of the CK (falling edges of the /CK), Data,
Data strobes and Write data masks inputs are sampled on both rising and falling edges of it. The data paths are inter-
nally pipelined and 2-bit prefetched to achieve very high bandwidth. All input and output voltage levels are compatible
with SSTL_2.
FEATURES
3.3V for V
DD
and 2.5V for V
DDQ
power supply
All inputs and outputs are compatible with SSTL_2
interface
JEDEC standard 400mil 66pin TSOP-II with 0.65mm
pin pitch
Fully differential clock inputs (CK, /CK) operation
Double data rate interface
Source synchronous - data transaction aligned to
bidirectional data strobe (DQS)
x16 device has 2 bytewide data strobes (LDQS,
UDQS) per each x8 I/O
Data outputs on DQS edges when read (edged DQ)
Data inputs on DQS centers when write (centered
DQ)
Data(DQ) and Write masks(DM) latched on the both
rising and falling edges of the data strobe
All addresses and control inputs except Data, Data
strobes and Data masks latched on the rising edges
of the clock
Write mask byte controls by LDM and UDM
/CAS Latency 3 supported
Programmable Burst Length 2 / 4 / 8 with both
sequential and interleave mode
Internal 4 bank operations with single pulsed /RAS
Auto refresh and self refresh supported
4096 refresh cycles / 64ms
Full and Half strength driver option controlled by
EMRS
ORDERING INFORMATION
Part No.
Power Supply
Clock
Frequency
Max Data Rate
interface
Package
HY5DV281622AT-5
V
DD
=3.3V
V
DDQ
=2.5V
200MHz
400Mbps/pin
SSTL_2
400mil 66pin
TSOP-II
HY5DV281622AT-43
233MHz
466Mbps/pin
HY5DV281622AT
Rev. 0.3/May. 02 3
相关PDF资料 |
PDF描述 |
|---|---|
| HY5PS121623F | 32Mx16|1.8V|8K|D43/D44/D54/D55|DDR II SDRAM - 512M |
| HY5PS121623LF | 32Mx16|1.8V|8K|D43/D44/D54/D55|DDR II SDRAM - 512M |
| HY5PS12423F | 128Mx4|1.8V|8K|D43/D44/D54/D55|DDR II SDRAM - 512M |
| HY5PS12423LF | 128Mx4|1.8V|8K|D43/D44/D54/D55|DDR II SDRAM - 512M |
| HY5PS12823F | 64Mx8|1.8V|8K|D43/D44/D54/D55|DDR II SDRAM - 512M |
相关代理商/技术参数 |
参数描述 |
|---|---|
| HY5DW113222FM | 制造商:HYNIX 制造商全称:Hynix Semiconductor 功能描述:512M(16Mx32) GDDR SDRAM |
| HY5DW113222FM-2 | 制造商:HYNIX 制造商全称:Hynix Semiconductor 功能描述:512M(16Mx32) GDDR SDRAM |
| HY5DW113222FM-22 | 制造商:HYNIX 制造商全称:Hynix Semiconductor 功能描述:512M(16Mx32) GDDR SDRAM |
| HY5DW113222FM-25 | 制造商:HYNIX 制造商全称:Hynix Semiconductor 功能描述:512M(16Mx32) GDDR SDRAM |
| HY5DW113222FM-28 | 制造商:HYNIX 制造商全称:Hynix Semiconductor 功能描述:512M(16Mx32) GDDR SDRAM |
发布紧急采购，3分钟左右您将得到回复。