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参数资料
| 型号： | HY5PS121623LF |
| 英文描述： | 32Mx16|1.8V|8K|D43/D44/D54/D55|DDR II SDRAM - 512M |
| 中文描述： | 32Mx16 | 1.8 | 8K的| D43/D44/D54/D55 |的DDR II内存- 512M |
| 文件页数： | 15/66页 |
| 文件大小： | 862K |
| 代理商： | HY5PS121623LF |
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Rev. 0.52/Nov. 02 15
HY5PS12423(L)F
HY5PS12823(L)F
HY5PS121623(L)F
Clock Enable (CKE) TRUTH TABLE for Synchronous Transitions
Current State
2
CKE
Command (N)
3
RAS, CAS, WE, CS
Action (N)
3
Notes
Previous Cycle
1
(N-1)
Current Cycle
1
(N)
Power Down
L
L
x
Maintain Power-Down
13, 15
L
H
DESELECT or NOP
Power Down Exit
4, 8
Self Refresh
L
L
x
Maintain Self Refresh
15
L
H
DESELECT or NOP
Self Refresh Exit
4, 5, 9
Bank(s) Active
H
L
DESELECT or NOP
Active Power Down Entry
4, 8, 10, 11
All Banks Idle
H
L
DESELECT or NOP
Precharge Power Down Entry
4, 8, 10
H
L
AUTOREFRESH
Self Refresh Entry
6, 9, 11
Any other state
H
H
Refer to the Command Truth Table
7
Notes:
1. CKE (N) is the logic state of CKE at clock edge N; CKE (N–1) was the state of CKE at the previous clock edge.
2. Current state is the state of the DDR SDRAM immediately prior to clock edge N.
3. COMMAND (N) is the command registered at clock edge N, and ACTION (N) is a result of COMMAND (N).
4. All states and sequences not shown are illegal or reserved unless explicitely described elsewhere in this document.
5. On Self Refresh Exit DESELECT or NOP commands must be issued on every clock edge occurring during the t
XSNR
period.
Read commands may be issued only after t
XSRD
(200 clocks) is satisfied.
6. Self Refresh mode can only be entered from the All Banks Idle state.
7. Must be a legal command as defined in the Command Truth Table.
8. Valid commands for Power Down Entry and Exit are NOP and DESELECT only.
9. Valid commands for Self Refresh Entry and Exit are NOP and DESELECT only.
10. Power Down and Self Refresh can not be entered while Read or Write operations, (Extended) Mode Register Set operations or
Precharge or Refresh operations are in progress. See section 2.2.9 "Power Down" and 2.2.8 "Self Refresh Command" for a
detailed list of restrictions.
11. Minimum CKE high time is tbd.; minimum CKE low time is tbd. (subject to separate ballot)
12. The state of ODT does not affect the states described in this table. The ODT function is not available during Self Refresh.
13. The Power Down does not perform any refresh operations. The duration of Power Down Mode is therefore limited by the
refresh requirements outlined in section (will be defined)
14. CKE must be maintained high while the SDRAM is in OCD calibration mode i.e. if any of the bits A7, A8, A9 in EMRS(1) are set
to "1".
15. “X” means “don’t care (including floating around VREF)” in Self Refresh and Power Down. However ODT must be driven high
or low in Power Down if the ODT fucntion is enabled (Bit A2 or A6 set to “1” in EMRS(1) ).
相关PDF资料 |
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| HY5PS12423F | 128Mx4|1.8V|8K|D43/D44/D54/D55|DDR II SDRAM - 512M |
| HY5PS12423LF | 128Mx4|1.8V|8K|D43/D44/D54/D55|DDR II SDRAM - 512M |
| HY5PS12823F | 64Mx8|1.8V|8K|D43/D44/D54/D55|DDR II SDRAM - 512M |
| HY5PS12823LF | 64Mx8|1.8V|8K|D43/D44/D54/D55|DDR II SDRAM - 512M |
| HY5P | Current Transducers HY 5 to 25-P/SP1 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| HY5PS12421AF | 制造商:HYNIX 制造商全称:Hynix Semiconductor 功能描述:512Mb DDR2 SDRAM |
| HY5PS12421AF-C3 | 制造商:HYNIX 制造商全称:Hynix Semiconductor 功能描述:512Mb DDR2 SDRAM |
| HY5PS12421AF-C4 | 制造商:HYNIX 制造商全称:Hynix Semiconductor 功能描述:512Mb DDR2 SDRAM |
| HY5PS12421AF-E3 | 制造商:HYNIX 制造商全称:Hynix Semiconductor 功能描述:512Mb DDR2 SDRAM |
| HY5PS12421AFP | 制造商:HYNIX 制造商全称:Hynix Semiconductor 功能描述:512Mb DDR2 SDRAM |
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