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参数资料
| 型号： | HY62256ALLT1-55 |
| 英文描述： | x8 SRAM |
| 中文描述： | x8的SRAM |
| 文件页数： | 6/9页 |
| 文件大小： | 144K |
| 代理商： | HY62256ALLT1-55 |
HY62256A Series
Rev.02 /Jun.99
6
WRITE CYCLE 2 (/OE Low Fixed)
tDW
tWHZ
WE
Data Valid
tDH
tWP
tAS
Data In
tWR
tCW
tAW
(7)
(8)
tOW
ADDR
CS
Data
Out
tWC
Notes(WRITE CYCLE):
1. A write occurs during the overlap of a low /CS and a low /WE. A write begins at the latest transition
among /CS going low and /WE going low: A write ends at the earliest transition among /CS going high
and /WE going high. tWP is measured from the beginning of write to the end of write.
2. tCW is measured from the later of /CS going low to the end of write .
3. tAS is measured from the address valid to the beginning of write.
4. tWR is measured from the end of write to the address change. tWR is applied in case a write ends as /CS,
or /WE going high.
5. If /OE and /WE are in the read mode during this period, and the I/O pins are in the output low-Z state,
input of opposite phase of the output must not be applied because bus contention can occur.
6. If /CS goes low simultaneously with /WE going low, or after /WE going low, the outputs remain in high
impedance state.
7. DOUT is the same phase of latest written data in this write cycle.
8. DOUT is the read data of the new address.
DATA RETENTION CHARACTERISTIC
Symbol
Parameter
Test Condition
Min
Typ
Max
Unit
VDR
Vcc for Data Retention
/CS >Vcc-0.2V,Vss<VIN<Vcc
2
-
V
ICCDR
Data Retention Current
Vcc = 3.0V, /CS > Vcc –0.2V
L
-
1
50
uA
Vss<VIN<Vcc
LL
-
1
15(2)
uA
tCDR
Chip Disable to Data
Retention Time
See Data Retention Timing
Diagram
0
-
ns
tR
Operating Recovery Time
tRC(3)
-
ns
Notes
1. Typical values are under the condition of TA = 25
°C.
2. 3uA max. at TA=0
°C to 40 °C.
3. tRC is read cycle time.
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