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参数资料
| 型号： | HY628100AT1 |
| 厂商： | Hynix Semiconductor Inc. |
| 英文描述： | 128Kx8bit CMOS SRAM |
| 中文描述： | 128Kx8bit CMOS SRAM的 |
| 文件页数： | 7/9页 |
| 文件大小： | 128K |
| 代理商： | HY628100AT1 |
HY628100A Series
Rev.05 /Feb.99
7
WRITE CYCLE 3 (CS2 Controlled)
ADDR
CS1
CS2
Data
Out
Data Valid
tWC
tWP
tCLZ
tCW
tAW
tAS
tDH
High-Z
tWR
tWHZ
tDW
High-Z
High-Z
Data In
WE
Notes(WRITE CYCLE):
1. A write occurs during the overlap of a low /CS1, CS2 and low /WE. A write begines at the latest transition
among /CS1 going low, CS2 going high and /WE going low: A write ends at the earliest transition among
/CS1 going high, CS2 low and /WE going high. tWP is measured from the beginning of write to the end of
write. .
2. tCW is measured from the later of /CS1 going low or CS2 going high to the end of write .
3. tAS is measured from the address valid to the beginning of write.
4. tWR is measured from the end of write to the address change. tWR is applied in case a write ends as
/CS1, or /WE going high, and tWR is applied in case a write ends at CS2 going low.
5. If /OE, CS2 and /WE are in the read mode during this period, the I/O pins are in the output low-Z state,
input of opposite phase of the output must not be applied because bus contention can occur.
6. If /CS1 goes low simultaneously with /WE going low, the outputs remain in high impedance state.
7. Dout is the read data of the new address.
8. When /CS1 is low and CS2 is high, I/O pins are in the output state. The input signals in the opposite
phase leading to the outputs should not be applied.
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| HY628100BLG-I | 128K x8 bit 5.0V Low Power CMOS slow SRAM |
| HY628100BLLT1 | 128K x8 bit 5.0V Low Power CMOS slow SRAM |
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相关代理商/技术参数 |
参数描述 |
|---|---|
| HY628100AT1-10 | 制造商:未知厂家 制造商全称:未知厂家 功能描述:x8 SRAM |
| HY628100AT1-55 | 制造商:未知厂家 制造商全称:未知厂家 功能描述:x8 SRAM |
| HY628100AT1-70 | 制造商:未知厂家 制造商全称:未知厂家 功能描述:x8 SRAM |
| HY628100AT1-85 | 制造商:未知厂家 制造商全称:未知厂家 功能描述:x8 SRAM |
| HY628100B | 制造商:HYNIX 制造商全称:Hynix Semiconductor 功能描述:128K x8 bit 5.0V Low Power CMOS slow SRAM |
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