参数资料
型号: HYS64V32220GU-7-C2
厂商: INFINEON TECHNOLOGIES AG
元件分类: DRAM
英文描述: 32M X 64 SYNCHRONOUS DRAM MODULE, 5.4 ns, DMA168
封装: DIMM-168
文件页数: 4/20页
文件大小: 322K
代理商: HYS64V32220GU-7-C2
HYS 64/72V16300/32220GU
SDRAM-Modules
INFINEON Technologies
12
9.01
SPD-Table for PC133-222 Modules:
Byte#
Description
SPD Entry
Value
Hex
16Mx64
-7
16Mx72
-7
32Mx64
-7
32Mx72
-7
0
Number of SPD bytes
128
80
1
Total bytes in Serial PD
256
08
2
Memory Type
SDRAM
04
3
Number of Row Addresses
(without BS bits)
12
0C
4
Number of Column Addres-
ses
10
0A
5
Number of DIMM Banks
1 / 2
01
02
6
Module Data Width
64 / 72
40
48
40
48
7
Module Data Width (cont’d)
0
00
8
Module Interface Levels
LVTTL
01
9
SDRAM Cycle Time at CL=3
7.5 ns
75
10
SDRAM Access time from
Clock at CL=3
5.4 ns
54
11
Dimm Config
none / ECC
00
02
00
02
12
Refresh Rate/Type
Self-Refresh,
15.6 s
80
13
SDRAM width,Primary
x8
08
14
Error Checking SDRAM data
width
n/a / x8
00
08
00
08
15
Minimum clock delay for
back-to-back random column
address
t
ccd = 1 CLK
01
16
Burst Length supported
1, 2, 4 & 8
0F
17
Number of SDRAM banks
4
04
18
Supported CAS Latencies
CAS latency = 2
& 3
06
19
CS Latencies
CS latency = 0
01
20
WE Latencies
Write latency = 0
01
21
SDRAM DIMM module
attributes
non buffered/non
reg.
00
22
SDRAM Device Attributes
:General
Vcc tol +/- 10%
0E
23
Min. Clock Cycle Time at
CAS Latency = 2
7.5 ns
75
24
Max. data access time from
Clock for CL=2
5.4 ns
54
25
Minimum Clock Cycle Time
at CL = 1
not supported
FF
26
Maximum Data Access Time
from Clock at CL=1
not supported
FF
27
Minimum Row Precharge
Time
15 ns
0F
28
Minimum Row Active to Row
Active delay tRRD
14 ns
0E
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