参数资料
型号: IA82527-PLC44A-R
厂商: Innovasic Semiconductor
英文描述: Serial Communications Controller CAN Protocol
中文描述: 串行通信控制器的CAN协议
文件页数: 14/45页
文件大小: 1760K
代理商: IA82527-PLC44A-R
IA82527
CAN Serial Communications Controller
As of Production Ver. 00
PRELIMINARY
Table 3. IA82527 Pin/Signal Descriptions
,
continued
04 May 2007
Copyright
2007
EN21070504-00
www.Innovasic.com
Customer Support:
Page 14 of 45
1-888-824-4184
Pin
Signal
Name
PLCC
QFP
Description
p1.0
p1.1
p1.2
p1.3
p1.4
p1.5
p1.6
p1.7
p2.0
p2.1
p2.2
p2.3
p2.4
p2.5
p2.6
p2.7
ad8/d0/
p1.0
38
32
ad9/d1/
p1.1
37
31
ad10/d2/
p1.2
36
30
ad11/d3/
p1.3
35
29
ad12/d4/
p1.4
34
28
ad13/d5/
p1.5
33
27
ad14/d6/
p1.6
32
26
ad15/d7/
p1.7
31
25
p
ort
1
, bit
N
(N = 7–0). Input/Output (general-purpose). Mode 0,
Mode 2, and Serial Interface Mode.
Port 1 bits
p1.7
p1.0
can be individually programmed as inputs or
outputs. Programming is accomplished by writing to the P1CONF
Register (9FH). The 8 bits of the P1CONF Register, P1CONF7–
P1CONF0, correspond directly to pins
p1.7
p1.0
. Writing a 0 to a bit
in the P1CONF Register causes the corresponding pin to be
configured as a high-impedance input. Writing a 1 to a bit in the
P1CONF Register causes the corresponding pin to be configured as
a push-pull output. All Port 1 pins have weak pull-ups until the port is
configured by writing to the P1CONF Register. The default value of
the P1CONF Register following a reset is 00H.
Data are read from Port 1 via the P1IN Register (BFH). A logic 0 for
any bit in this register means that a logic 0 was read from the
corresponding pin; a logic 1 for any bit means that a logic 1 was read
from the corresponding pin. The default value of the P1IN Register
following a reset is FFH.
Data are written to Port 1 via the P1OUT Register (DFH). Writing a
logic 0 to any bit in this register means that a logic 0 is written to the
corresponding pin; writing a logic 1 to any bit means that a logic 1 is
written to the corresponding pin. The default value of the P1OUT
Register following a reset is 00H.
17
11
16
10
15
9
14
8
13
7
12
6
int_n/
p2.6
11
5
wrh_n/
p2.7
10
4
p
ort
2
, bit
N
(N = 7–0). Input/Output.
Port 2 bits
p2.7
p2.0
, can be individually programmed as inputs or
outputs. Programming is accomplished by writing to the P2CONF
Register (AFH). The 8 bits of the P2CONF Register, P2CONF7–
P2CONF0, correspond directly to pins
p2.7
p2.0
. Writing a 0 to a bit
in the P2CONF Register causes the corresponding pin to be
configured as a high-impedance input. Writing a 1 to a bit in the
P2CONF Register causes the corresponding pin to be configured as
a push-pull output. All Port 2 pins have weak pull-ups until the port is
configured by writing to the P2CONF Register. The default value of
the P1CONF Register following a reset is 00H.
Data are read from Port 2 via the P2IN Register (CFH). A logic 0 for
any bit in this register means that a logic 0 was read from the
corresponding pin; a logic 1 for any bit means that a logic 1 was read
from the corresponding pin. The default value of the P2IN Register
following a reset is FFH.
Data are written to Port 2 via the P2OUT Register (EFH). Writing a
logic 0 to any bit in this register means that a logic 0 is written to the
corresponding pin; writing a logic 1 to any bit means that a logic 1 is
written to the corresponding pin. The default value of the P2OUT
Register following a reset is 00H.
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