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| 型号： | IA82527-PTQ44A |
| 厂商： | Innovasic Semiconductor |
| 英文描述： | Serial Communications Controller CAN Protocol |
| 中文描述： | 串行通信控制器的CAN协议 |
| 文件页数： | 15/45页 |
| 文件大小： | 1760K |
| 代理商： | IA82527-PTQ44A |
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IA82527
CAN Serial Communications Controller
As of Production Ver. 00
PRELIMINARY
04 May 2007
Copyright
2007
EN21070504-00
www.Innovasic.com
Customer Support:
Page 15 of 45
1-888-824-4184
continued
. . .
Table 3. IA82527 Pin/Signal Descriptions
,
continued
Pin
Signal
Name
PLCC
QFP
Description
rd_n
rd_n
/e
6
44
r
ea
d
. Input. Active Low. Mode 0 and Mode 1.
When
rd_n
is asserted (low), it causes the IA82527 to drive the data
from the location being read onto the data bus.
ready
. Output (open drain). Active High. Mode 0 and Mode 1.
When ready is asserted (high), it signals the completion of a bus
cycle. The ready output is provided to force system CPU wait states
as required.
reset
. Input. Active Low.
When the
reset_n
signal is asserted (low), the IA82527 is initialized.
There are two reset situations:
Cold Reset. This is a power-on reset: As V
CC
is driven to a valid
level (power on), the
reset_n
signal must be driven low for a
minimum of 1 ms measured from a valid V
CC
level. No falling edge
on the reset_n pin is required during a cold reset.
Warm Reset. For this reset, V
CC
remains at a valid level (i.e., power
is already on and remains on) while
reset_n
is driven low for a
minimum of 1 ms.
r
ead
-w
rite. Input. Active High (read)-Active Low (write). Mode 3.
When
r-w_n
is high, it signals a read cycle. When
r-w_n
is low, it
signals a write cycle.
Receive (
rx
), lines
0
and
1
. Input.
Pins
rx0
and
rx1
are the inputs to the IA82527 from the Controller
Area Network (CAN) bus lines. These pins connect internally to the
receiver input comparator. Serial data from the CAN bus can be
received using both
rx0
and
rx1
or by using only
rx0
as follows:
When the CoBy Bit in the Bus Configuration Register (2FH) is
a 0,
rx0
and
rx1
are connected to the input comparator. (
rx0
is connected to the non-inverting input and rx1 is connected
to the inverting input.) A recessive level is read when
rx0
>
rx1
. A dominant level is read when
rx1
>
rx0
.
When the CoBy Bit in the Bus Configuration Register (2FH) is
a 1, input comparison is disabled, and
rx0
, which is still
connected to the non-inverting input of the comparator, is the
CAN bus line input. For this configuration, the DcR0 bit of the
Bus Configuration Register must be a 0.
After a cold reset (power on), the default configuration is the use of
both
rx0
and
rx1
for the CAN bus input.
s
erial
cl
oc
k
. Input. Serial Interface Mode.
The
sclk
pin is the serial clock input to the IA82527 (slave device).
The clock signal is provided by the master device.
ready
ready
/miso
28
22
reset_n
—
29
23
r-w_n
wr
_
n/wrl
_
n/
r-w
_
n
7
1
rx0
—
22
16
rx1
—
21
15
sclk
a6/ad6/
sclk
40
34
continued
. . .
相关PDF资料 |
PDF描述 |
|---|---|
| IA82527-PTQ44A-R | Serial Communications Controller CAN Protocol |
| IA88C00 | Microcontroller |
| IA88C00-PDW48C | Microcontroller |
| IA88C00-PDW48C-R | Microcontroller |
| IA88C00-PDW48I | Microcontroller |
相关代理商/技术参数 |
参数描述 |
|---|---|
| IA82527-PTQ44A-R | 制造商:INNOVASIC 制造商全称:INNOVASIC 功能描述:Serial Communications Controller CAN Protocol |
| IA8255 | 制造商:INNOVASIC 制造商全称:INNOVASIC 功能描述:Programmable Peripheral Interface Adapter |
| IA8255-PDW40C | 制造商:INNOVASIC 制造商全称:INNOVASIC 功能描述:Programmable Peripheral Interface Adapter |
| IA8255-PDW40I | 制造商:INNOVASIC 制造商全称:INNOVASIC 功能描述:Programmable Peripheral Interface Adapter |
| IA8255-PLC44C | 制造商:INNOVASIC 制造商全称:INNOVASIC 功能描述:Programmable Peripheral Interface Adapter |
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