参数资料
型号: IA82527
厂商: Innovasic Semiconductor
英文描述: Serial Communications Controller CAN Protocol
中文描述: 串行通信控制器的CAN协议
文件页数: 12/45页
文件大小: 1760K
代理商: IA82527
IA82527
CAN Serial Communications Controller
As of Production Ver. 00
PRELIMINARY
Table 3. IA82527 Pin/Signal Descriptions
,
continued
04 May 2007
Copyright
2007
EN21070504-00
www.Innovasic.com
Customer Support:
Page 12 of 45
1-888-824-4184
Pin
Signal
Name
PLCC
QFP
Description
dsack0_n
9
3
d
ata and
s
ize
ack
nowledge
0
. Output. Active Low (open drain with
active pull-up). Mode 3 (asynchronous operation).
When the IA82527 is configured to operate in the 8-bit non-
multiplexed non-Intel
architecture mode (Mode 3), this signal
functions as follows: when the CPU reads from the IA82527,
dsack0_n
active low indicates that the data are valid; when the CPU
writes to the IA82527,
dsack0_n
active low indicates that the data
have been received.
e
nable. Input. Active High. Mode 3 (asynchronous).
When the IA82527 is configured to operate in the 8-bit non-
multiplexed non-Intel
architecture mode (Mode 3), this signal
functions as follows: when the CPU reads from or writes to the
IA82527,
e
active high indicates that the address is valid.
i
dle
c
lock
p
olarity. Input. Serial Interface Mode.
When this input is a logic 0, the polarity for the idle state of
sclk
is
low. When this input is a logic 1, the polarity for the idle state of
sclk
is high.
int
errupt. Output (open collector). Active Low.
On the IA82527, two pins can provide the interrupt (
int_n
) output;
however, depending on the setting of the MUX bit in the CPU
Interface Register (02H), only one of the pins will serve as the source
of
int_n
as follows:
PLCC Package:
-
When the MUX bit of the CPU Interface Register is 0, pin
24 functions as the
int_n
output and pin 11 functions as
p2.6
.
-
When the MUX bit of the CPU Interface Register is 1, pin
11 functions as the
int_n
output and pin 24 functions as
V
cc
/2
.
QFP Package:
-
When the MUX bit of the CPU Interface Register is 0, pin
18 functions as the
int_n
output and pin 5 functions as
p2.6
.
-
When the MUX bit of the CPU Interface Register is 1, pin
5 functions as the
int_n
output and pin 18 functions as
V
cc
/2
.
e
rd_n/
e
6
44
icp
a0/ad0/
icp
4
42
int_n
/ V
CC
/2
24
18
int_n
int_n
/p2.6
11
5
continued
. . .
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