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参数资料
| 型号： | IBM04364ARLAD-5N |
| 元件分类： | SRAM |
| 英文描述： | 128K X 36 STANDARD SRAM, 5.5 ns, PBGA119 |
| 封装： | BGA-119 |
| 文件页数： | 1/22页 |
| 文件大小： | 517K |
| 代理商： | IBM04364ARLAD-5N |
75H4338
Revised 2/99
IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 1 of 22
IBM04184ARLAD
IBM04364ARLAD
Preliminary
128K x 36 & 256K x 18 SRAM
Features
128K x 36 or 256K x 18 Organizations
CMOS Technology
Synchronous Register-Latch Mode Of Opera-
tion with Self-Timed Late Write
Single Differential PECL Clock compatible with
LVTTL Levels
+3.3V Power Supply, VDDQ & Ground
Common I/O & LVTTL I/O Compatible
Registered Addresses, Write Enables, Synchro-
nous Select and Data Ins
Latched Outputs
Asynchronous Output Enable and Power Down
Inputs
Boundary Scan using limited set of JTAG
1149.1 functions
Byte Write Capability & Global Write Enable
7 x 17 Bump Ball Grid Array Package with
SRAM JEDEC Standard Pinout and Boundary
SCAN Order.
Description
The IBM04184ARLAD and IBM04364ARLAD 4Mb
SRAMS are Synchronous Register-Latch Mode,
high performance CMOS Static Random Access
Memories that are versatile, wide I/O, and achieve
6ns cycle and 5.5ns access times. Dual differential
K clocks are used to initiate the read/write operation
and all internal operations are self-timed. At the ris-
ing edge of the K Clock, all Addresses, Write-
Enables, Sync Select, and Data Ins are registered
internally. Data Outs are updated from output
latches off the falling edge of the K Clock. An inter-
nal Write buffer allows write data to follow one cycle
after addresses and controls. The chip is operated
with a +3.3V power supply, has a 2.5V or 3.3V Out-
put Power Supply, and is compatible with LVTTL I/O
interfaces.
.
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