参数资料
型号: IBM25NPE405H-3BA266CZ
元件分类: 微控制器/微处理器
英文描述: 32-BIT, 266 MHz, RISC PROCESSOR, PBGA580
封装: 35 MM, PLASTIC, EBGA-580
文件页数: 37/74页
文件大小: 1423K
代理商: IBM25NPE405H-3BA266CZ
Preliminary
PowerNP NPe405H Embedded Processor Data Sheet
42
Signal Description
The following table provides a summary of the number of package pins (balls) associated with each functional
interface group.
Multiplexed pins
In the table “Signal Functional Description” on page 44, each external signal is listed along with a short
description of the signal function. The signals are grouped together according to their function. Some signals
are multiplexed on the same package pin (ball) so that the pin can be used for different functions. In most
cases, the signal name is shown in this table unaccompanied by multiplexed signal names that may be
associated with it. In cases where multiplexed signals are in the same functional group, the names appear as
a default signal followed by secondary signals in square brackets (for example, EMC0TxErr[EMC0Tx1En]).
Active-low signals (for example, RAS) are marked with an overline. Any signal that is not the primary (default)
signal on a multiplexed pin is shown in square brackets.
The active signal on a multiplexed pin is controlled by programming. It is expected that in any single
application, a particular pin will always be programmed to serve the same function. The flexibility of
multiplexing allows a single chip to offer a richer pin selection than would otherwise be possible.
Multipurpose pins
In addition to multiplexing, pins may also be multipurpose. An example of multi-purpose use occurs when the
EBC peripheral controller address pins are used as outputs by the NPe405H to broadcast an address to
external slave devices when the NPe405H has control of the external bus. However, when an external master
gains ownership of the external bus, these same pins are used as inputs which are driven by the external
master and received by the EBC in the NPe405H. In this example, the pins are also bidirectional, serving as
both inputs and outputs.
Initialization Strapping
One group of pins is used as strapped inputs during system reset. These pins function as strapped inputs
only during reset and are used for other functions during normal operation (see “Initialization” on page 71).
Note that the use of these pins for strapping is not considered multiplexing since the strapping function is not
programmable.
Pin Summary
Group
No. of Pins
Nonmultiplexed Signals
256
Multiplexed Signals
85
Total Signal Pins
341
AVDD
1
OVDD
49
VDD
24
Gnd
65
Gnd (and thermal)
100
Reserved
0
Total Pins
580
相关PDF资料
PDF描述
IBM25NPE405H-3DA200CZ 32-BIT, 200 MHz, RISC PROCESSOR, PBGA580
IBM25NPE405L-3DA200CZ 32-BIT, 200 MHz, RISC PROCESSOR, PBGA324
IBM25NPE405L-3FA200CZ 32-BIT, 200 MHz, RISC PROCESSOR, PBGA324
IBM25NPE405L-3FA266CZ 32-BIT, 266 MHz, RISC PROCESSOR, PBGA324
IBM25PPC405EP-3GB133CZ 32-BIT, 133.33 MHz, RISC PROCESSOR, PBGA385
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