![](http://datasheet.mmic.net.cn/100000/IBM25PPC405GPR-3BA333CZ_datasheet_3492225/IBM25PPC405GPR-3BA333CZ_46.png)
Preliminary
PowerPC 405GPr Embedded Processor Data Sheet
46
Notes: 1. In all of the following I/O Specifications tables a timing values of na means “not applicable” and dc
means “don’t care.”
I/O Specifications—Group 1 (Part 1 of 3)
Notes:
1. PCI timings are for asynchronous operation up to 66.66MHz. PCI output hold time requirement is 1ns for 66.66MHz
and 2ns for 33.33MHz.
2. Ethernet interface meets timing requirements as defined by IEEE 802.3 standard.
3. For PCI, I/O H is specified at 0.9OVDD and I/O L is specified at 0.1OVDD. For all other interfaces, I/O H is specified at
2.4 V and I/O L is specified at 0.4 V.
Signal
Input (ns)
Output (ns)
Output Current (mA)
Clock
Notes
Setup Time
(TIS min)
Hold Time
(TIH min)
Valid Delay
(TOV max)
Hold Time
(TOH min)
I/O H
(min)
I/O L
(min)
PCI Interface
PCIAD31:0
3
0
6
1
0.5
1.5
PCIClk
1
PCIC3:0[BE3:0]
3
0
6
1
0.5
1.5
PCIClk
1
PCIClk
dc
na
async
PCIDevSel
3
0
6
1
0.5
1.5
PCIClk
1
PCIFrame
3
0
6
1
0.5
1.5
PCIClk
1
PCIGnt0[Req]
PCIGnt1:5
na
6
1
0.5
1.5
PCIClk
1
PCIIDSel
3
0
6
1
na
PCIClk
1
PCIINT[PerWE]
na
dc
0.5
1.5
PCIClk
async
PCIIRDY
3
0
6
1
0.5
1.5
PCIClk
1
PCIParity
3
0
6
1
0.5
1.5
PCIClk
1
PCIPErr
3
0
6
1
0.5
1.5
PCIClk
1
PCIReq0[Gnt]
PCIReq1:5
5
0
na
PCIClk
1
PCIReset
na
0.5
1.5
PCIClk
PCISErr
na
0.5
1.5
PCIClk
PCIStop
3
0
6
1
0.5
1.5
PCIClk
1
PCITRDY
3
0
6
1
0.5
1.5
PCIClk
1
Ethernet Interface
EMCMDClk
na
settable
2
10.3
7.1
2, async
EMCMDIO[PHYMDIO]
100
0
1 OPB clock
period + 10ns
1 OPB clock
period
10.3
7.1
EMCMDClk
2
EMCTxD3:0
na
20
2
10.3
7.1
PHYTX
2
EMCTxEn
na
20
2
10.3
7.1
PHYTX
2
EMCTxErr
na
20
2
10.3
7.1
PHYTX
2
PHYCol
10.3
7.1
2, async
PHYCrS
10.3
7.1
2, async
PHYRxClk
na
2, async
PHYRxD3:0
4
1
na
10.3
7.1
PHYRX
2
PHYRxDV
4
1
na
10.3
7.1
PHYRX
2
PHYRxErr
4
1
na
10.3
7.1
PHYRX
2
PHYTxClk
na
2, async